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Commit Graph

139622 Commits

Author SHA1 Message Date
Mehdi Amini
fc6ad6010e Add computeHostNumPhysicalCores() implementation for Darwin
Differential Revision: https://reviews.llvm.org/D25800

llvm-svn: 284656
2016-10-19 22:36:07 +00:00
Wei Ding
dba32d5baf AMDGPU : Add a function to enable and disable IEEEBit for SC and shader
respectively.

Differential Revision: http://reviews.llvm.org/D25789

llvm-svn: 284655
2016-10-19 22:34:49 +00:00
Lang Hames
67a8bd8552 Remove the JIT EH/small code model tests for now.
These tests rely on two sections being allocated with a limited displacement
from one to the other to work. We've never guaranteed this, and consequently
these tests usually fail. That led to them being XFAILed, but now they XPASS
whenever the sections do happen to be allocated nearby in memory. So I'm
removing these for now to get rid of the noise. We can re-instate them if/when
we take the time to implement a displacement-respecting allocator.

llvm-svn: 284654
2016-10-19 22:19:38 +00:00
Chris Bieneman
212dec866c [CMake] Make the runtimes directory work with bootstrap builds
This patch builds on clang r284648, and allows the runtime directory to make the bootstrap builds depend on the builtin libraries.

This patch also make the bootstrap build depend on configuring the other runtimes because the libcxx headers are copied during configuration. I have left a TODO in the code to remove that once I come up with a better solution.

llvm-svn: 284650
2016-10-19 21:50:25 +00:00
Sanjay Patel
4b2cca44ae [InstSimplify] fold negation of sign-bit
0 - X --> X, if X is 0 or the minimum signed value
0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW

I noticed this pattern might be created in the backend after the change from D25485, 
so we'll want to add a similar fold for the DAG.

The use of computeKnownBits in InstSimplify may be something to investigate if the
compile time of InstSimplify is noticeable. We could replace computeKnownBits with 
specific pattern matchers or limit the recursion.

Differential Revision: https://reviews.llvm.org/D25785

llvm-svn: 284649
2016-10-19 21:23:45 +00:00
Lang Hames
e7f3450978 [BuildingAJIT] Make the chapter 5 server export symbols.
This will allow chapter 5 to work on Linux.

llvm-svn: 284637
2016-10-19 20:22:12 +00:00
Hans Wennborg
51b63008cc Typo: nomed struct -> named struct
llvm-svn: 284635
2016-10-19 20:10:03 +00:00
Reid Kleckner
dcf108e176 [GlobalMerge] Handle non-landingpad EH pads
This code crashed on funclet-style EH instructions such as catchpad,
catchswitch, and cleanuppad. Just treat all EH pad instructions
equivalently and avoid merging the globals they reference through any
use.

llvm-svn: 284633
2016-10-19 19:56:22 +00:00
Artur Pilipenko
51d1f548b9 [IndVarSimplify] Teach calculatePostIncRange to take guards into account
Reviewed By: sanjoy

Differential Revision: https://reviews.llvm.org/D25739

llvm-svn: 284632
2016-10-19 19:43:54 +00:00
Matthew Simpson
f64cb1c3a7 [LV] Avoid emitting trivially dead instructions
Some instructions from the original loop, when vectorized, can become trivially
dead. This happens because of the way we structure the new loop. For example,
we create new induction variables and induction variable "steps" in the new
loop. Thus, when we go to vectorize the original induction variable update, it
may no longer be needed due to the instructions we've already created. This
patch prevents us from creating these redundant instructions. This reduces code
size before simplification and allows greater flexibility in code generation
since we have fewer unnecessary instruction uses.

Differential Revision: https://reviews.llvm.org/D25631

llvm-svn: 284631
2016-10-19 19:22:02 +00:00
Chad Rosier
d8727d0208 [AliasSetTracker] Add support for memcpy and memmove.
Differential Revision: https://reviews.llvm.org/D25776

llvm-svn: 284630
2016-10-19 19:09:03 +00:00
Artur Pilipenko
2bac40ee1c [IndVarSimplify] Use control-dependent range information to prove non-negativity
This change is motivated by the case when IndVarSimplify doesn't widen a comparison of IV increment because it can't prove IV increment being non-negative. We end up with a redundant trunc of the widened increment on this example.

for.body:
  %i = phi i32 [ %start, %for.body.lr.ph ], [ %i.inc, %for.inc ]
  %within_limits = icmp ult i32 %i, 64
  br i1 %within_limits, label %continue, label %for.end

continue:
  %i.i64 = zext i32 %i to i64
  %arrayidx = getelementptr inbounds i32, i32* %base, i64 %i.i64
  %val = load i32, i32* %arrayidx, align 4
  br label %for.inc

for.inc:
  %i.inc = add nsw nuw i32 %i, 1
  %cmp = icmp slt i32 %i.inc, %limit
  br i1 %cmp, label %for.body, label %for.end

There is a range check inside of the loop which guarantees the IV to be non-negative. NSW on the increment guarantees that the increment is also non-negative. Teach IndVarSimplify to use the range check to prove non-negativity of loop increments.

Reviewed By: sanjoy

Differential Revision: https://reviews.llvm.org/D25738

llvm-svn: 284629
2016-10-19 18:59:03 +00:00
Chad Rosier
7e82f2f969 [AliasSetTracker] Return void for add() functions. NFC.
Differential Revision: https://reviews.llvm.org/D25748

llvm-svn: 284628
2016-10-19 18:50:32 +00:00
Sanjay Patel
054119b163 [InstSimplify] move one and add more tests for potential negation folds
llvm-svn: 284627
2016-10-19 18:42:12 +00:00
Rafael Espindola
990d76cd41 Add a macro for prefetching data.
It will be used in lld.

llvm-svn: 284626
2016-10-19 18:34:32 +00:00
Mehdi Amini
f7a229fb6c [ADT] Zip range adapter
This augments the STLExtras toolset with a zip iterator and range
adapter. Zip comes in two varieties: `zip`, which will zip to the
shortest of the input ranges, and `zip_first`, which limits its
`begin() == end()` checks to just the first range.

Recommit r284035 after MSVC2013 support has been dropped.

Patch by: Bryant Wong <github.com/bryant>

Differential Revision: https://reviews.llvm.org/D23252

llvm-svn: 284623
2016-10-19 18:02:21 +00:00
Vedant Kumar
9b70342c33 [llvm-cov] Don't spawn a thread unless ThreadCount > 1
Initializing a ThreadPool with ThreadCount = 1 spawns a thread even
though we don't need to. This is at least slower than it needs to be,
and at worst may somehow be exacerbating PR30735 (llvm-cov times out
on ARM bots).

As a follow-up, I'll try to add logic to llvm::ThreadPool to avoid
spawning a thread when ThreadCount = 1.

llvm-svn: 284621
2016-10-19 17:55:44 +00:00
Krzysztof Parzyszek
f820888dd5 [AMDGPU] Stop using MCRegisterClass::getSize()
Differential Review: https://reviews.llvm.org/D24675

llvm-svn: 284619
2016-10-19 17:40:36 +00:00
Teresa Johnson
73f09465fc [ThinLTO] Default backend threads to heavyweight_hardware_concurrency
Summary:
Changes default backend parallelism from thread::hardware_concurrency to
the new llvm::heavyweight_hardware_concurrency, which for X86 Linux
defaults to the number of physical cores (and will fall back to
thread::hardware_concurrency otherwise). This avoid oversubscribing
the physical cores using hyperthreading.

Reviewers: mehdi_amini, pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25775

llvm-svn: 284618
2016-10-19 17:35:01 +00:00
Simon Pilgrim
7f0bc25e15 Merged nested ifs. NFCI.
llvm-svn: 284616
2016-10-19 17:30:24 +00:00
Pavel Labath
72bcdae4fb Revert "Add Chrono.h - std::chrono support header"
This reverts commit r284590 as it fails on the mingw buildbot. I think I know the
fix, but I cannot test it right now. Will reapply when I verify it works ok.

This reverts r284590.

llvm-svn: 284615
2016-10-19 17:17:53 +00:00
Simon Pilgrim
65abcecc2a [DAGCombiner] Add general constant vector support to (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

llvm-svn: 284613
2016-10-19 17:12:22 +00:00
Reid Kleckner
34c533658f [WinEH] Allow catchpads to reuse the same catch object
This code used a regular when it should have used a multimap.

llvm-svn: 284612
2016-10-19 17:08:23 +00:00
Sanjay Patel
b7d4502f35 [DAG] optimize negation of bool
Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG.
With the mask, this should be no worse than 2 shifts. The mask can be eliminated
in some cases, so that should be better than 2 shifts.

This change exposed some missing folds related to negation:
https://reviews.llvm.org/rL284239
https://reviews.llvm.org/rL284395

There may be others, so please let me know if you see any regressions.

Differential Revision: https://reviews.llvm.org/D25485

llvm-svn: 284611
2016-10-19 16:58:59 +00:00
Zachary Turner
cffe335315 [pdb] Improve error messages when DIA is not found.
llvm-svn: 284610
2016-10-19 16:42:20 +00:00
Krzysztof Parzyszek
f5fdbce361 [RDF] Switch RefMap in liveness calculation to use lane masks
This required reengineering of some of the part of liveness calculation,
including fixing some issues caused by the limitations of the previous
approach. The current code is not necessarily the fastest, but it should
be functionally correct (at least more so than before). The compile-time
performance will be addressed in the future.

llvm-svn: 284609
2016-10-19 16:30:56 +00:00
Simon Pilgrim
ff0b5288c1 [DAGCombiner] Add general constant vector support to (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

llvm-svn: 284608
2016-10-19 16:15:30 +00:00
Simon Pilgrim
4b04830ee0 [DAGCombiner] Add general constant vector support to (shl (mul x, c1), c2) -> (mul x, c1 << c2)
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

llvm-svn: 284607
2016-10-19 15:59:28 +00:00
Tim Northover
9484732ba1 Revert r284604. A.K.A. "TMP"
Committed by mistake.

llvm-svn: 284606
2016-10-19 15:56:12 +00:00
Tim Northover
239e4565e1 Sparc: fix test.
llvm-svn: 284605
2016-10-19 15:55:11 +00:00
Tim Northover
ac1f970b0a TMP
llvm-svn: 284604
2016-10-19 15:55:09 +00:00
Tim Northover
bf9fb9a96b GlobalISel: support translating volatile loads and stores.
llvm-svn: 284603
2016-10-19 15:55:06 +00:00
Artur Pilipenko
6a0a975738 Introduce ConstantRange.addWithNoSignedWrap
To be used by upcoming change to IndVarSimplify

Reviewed By: sanjoy

Differential Revision: https://reviews.llvm.org/D25732

llvm-svn: 284597
2016-10-19 14:44:23 +00:00
Chris Dewhurst
7e66f0654b [Sparc][LEON] Detects an erratum on UT699 LEON 3 processors involving rounding mode changes and issues an appropriate user error message.
Differential Revision: https://reviews.llvm.org/D24665

llvm-svn: 284591
2016-10-19 14:01:06 +00:00
Pavel Labath
79a60cfd95 Add Chrono.h - std::chrono support header
Summary:
std::chrono mostly covers the functionality of llvm::sys::TimeValue and
lldb_private::TimeValue. This header adds a bit of utility functions and
typedefs, which make the usage of the library and porting code from TimeValues
easier.

Rationale:
- TimePoint typedef - precision of system_clock is implementation defined -
  using a well-defined precision helps maintain consistency between platforms,
  makes it interact better with existing TimeValue classes, and avoids cases
  there a time point is implicitly convertible to a specific precision on some
  platforms but not on others.
- system_clock::to_time_t only accepts time_points with the default system
  precision (even though time_t has only second precision on all platforms we
  support). To avoid the need for explicit casts, I have added a toTimeT()
  wrapper function. toTimePoint(time_t) was not strictly necessary, but I have
  added it for symmetry.

Reviewers: zturner, mehdi_amini

Subscribers: beanz, mgorny, llvm-commits, modocache

Differential Revision: https://reviews.llvm.org/D25416

llvm-svn: 284590
2016-10-19 13:58:55 +00:00
Sjoerd Meijer
3d94a0d81d Reapply r284571 (with the new tests fixed).
llvm-svn: 284588
2016-10-19 13:43:02 +00:00
NAKAMURA Takumi
679c8175bd llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \xA0 in the test file.
It might crash FileCheck.

llvm-svn: 284587
2016-10-19 13:41:12 +00:00
Ulrich Weigand
947360bd07 [SystemZ] Add missing vector instructions for the assembler
Most z13 vector instructions have a base form where the data type of
the operation (whether to consider the vector to be 16 bytes, 8
halfwords, 4 words, or 2 doublewords) is encoded into a mask field,
and then a set of extended mnemonics where the mask field is not
present but the data type is encoded into the mnemonic name.

Currently, LLVM only supports the type-specific forms (since those
are really the ones needed for code generation), but not the base
type-generic forms.

To complete the assembler support and make it fully compatible with
the GNU assembler, this commit adds assembler aliases for all the
base forms of the various vector instructions.

It also adds two more alias forms that are documented in the PoP:
VFPSO/VFPSODB/WFPSODB -- generic form of VFLCDB etc.
VNOT -- special variant of VNO

llvm-svn: 284586
2016-10-19 13:03:18 +00:00
Ulrich Weigand
bbbc1ef6a8 [SystemZ] Add optional argument to some vector string instructions
The vfee[bhf], vfene[bhf], and vistr[bhf] assembler mnemonics are
documented in the Principles of Operation to have an optional last
operand to encode arbitrary values in a mask field.

This commit adds support for those optional operands, and cleans up
the patterns to generate vector string instruction as bit.  No change
to code generation intended.

llvm-svn: 284585
2016-10-19 12:57:46 +00:00
Michal Gorny
691da67fd3 [cmake] Declare LLVM_CMAKE_PATH for use in subprojects
Declare the LLVM_CMAKE_PATH to the source directory location of CMake
files, in order to make it possible to easily use them in subprojects.
Such a variable is already declared in most of LLVM projects
(and inconsistently mixed with direct source tree references), including
Clang, LLDB, compiler-rt, libcxx... Declaring it inside main LLVM tree
makes it possible to avoid having to declare fallback values or use
conditionals in those projects.

It should be noted that in some of the subprojects LLVM_CMAKE_PATH is
used to reference generated LLVMConfig.cmake file. However, these
references are conditional to stand-alone builds and explicitly
including this file is unnecessary in combined builds.

Differential Revision: https://reviews.llvm.org/D25724

llvm-svn: 284581
2016-10-19 12:18:34 +00:00
James Molloy
5a58c95fb7 [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables
The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions.

It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size.

TBB example:
Before: lsls r0, r0, #2    After: add  r0, pc
        adr  r1, .LJTI0_0         ldrb r0, [r0, #6]
        ldr  r0, [r0, r1]         lsls r0, r0, #1
        mov  pc, r0               add  pc, r0
  => No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4.

The only case that can increase dynamic instruction count is the TBH case:

Before: lsls r0, r4, #2    After: lsls r4, r4, #1
        adr  r1, .LJTI0_0         add  r4, pc
        ldr  r0, [r0, r1]         ldrh r4, [r4, #6]
        mov  pc, r0               lsls r4, r4, #1
                                  add  pc, r4
  => 1 more instruction in prologue. Jump table shrunk by a factor of 2.

So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!)

llvm-svn: 284580
2016-10-19 12:06:49 +00:00
Simon Pilgrim
b64dd46f6c [DAGCombiner] Just call isConstOrConstSplat directly. NFCI.
This will get the same ConstantSDNode scalar or vector splat value as the current separate dyn_cast<ConstantSDNode> / isVector() approach.

llvm-svn: 284578
2016-10-19 11:28:15 +00:00
Simon Pilgrim
b021eb5de6 Fix line endings
llvm-svn: 284576
2016-10-19 11:16:58 +00:00
Simon Pilgrim
872e4a47f8 [DAGCombine] Generalize distributeTruncateThroughAnd to work with any non-opaque constant or constant vector
llvm-svn: 284574
2016-10-19 08:57:37 +00:00
Sjoerd Meijer
6540326539 Revert of r284571 because of failing tests.
llvm-svn: 284572
2016-10-19 07:45:48 +00:00
Sjoerd Meijer
522c2a6a6a Checking FP function attribute values and adding more build attribute tests.
This renames the function for checking FP function attribute values and also
adds more build attribute tests (which are in separate files because build
attributes are set per file).

Differential Revision: https://reviews.llvm.org/D25625

llvm-svn: 284571
2016-10-19 07:25:06 +00:00
NAKAMURA Takumi
e8c4ba7c4c DenseSet: Appease msc18 to define derived constructors explicitly.
msc18 doesn't recognize "using BaseT::BaseT;"

  llvm\include\llvm/ADT/DenseSet.h(213) : error C2875: using-declaration causes a multiple declaration of 'BaseT'
          llvm\include\llvm/ADT/DenseSet.h(214) : see reference to class template instantiation 'llvm::DenseSet<ValueT,ValueInfoT>' being compiled
  llvm\include\llvm/ADT/DenseSet.h(231) : error C2875: using-declaration causes a multiple declaration of 'BaseT'
          llvm\include\llvm/ADT/DenseSet.h(232) : see reference to class template instantiation 'llvm::SmallDenseSet<ValueT,InlineBuckets,ValueInfoT>' being compiled

llvm-svn: 284570
2016-10-19 05:43:17 +00:00
Craig Topper
7301554d8d [AVX-512] Teach isel lowering that a subvector broadcast being inserted into both halves of a 512-bit vector can be combined into a larger subvector broadcast.
Summary:
This allows us to create broadcasts of 128-bit vector loads into 512-bit vectors.

New patterns added to support 8-bit and 16-bit vector types and v2f64/v2i64->v8f64/v8i64 without DQI instructions.

There also fallback patterns when the load can't be folded. These patterns are a little complex as we first need to insert the lower 128-bits into the second 128-bits using a zmm subvector insert instruction. We need to use a zmm insert in case VLX isn't available. Then use another zmm sub vector insert to take those 256-bits and insert them into the upper bits. Since we used a zmm insert to create the 256-bits we also need to do a extract_subreg to get just the lower 256-bits to pass to the second insert.

The outer insert for the fallback patterns should have its type correct because eventually we should also supported masked operations here too. So we need a DQI and a NoDQI version of the v16f32/v16i32 patterns.

Reviewers: RKSimon, delena, igorb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25651

llvm-svn: 284567
2016-10-19 04:44:17 +00:00
Dehao Chen
48514ff998 Update the section.ll to fix non-x86 failure.
llvm-svn: 284566
2016-10-19 03:53:41 +00:00
Dehao Chen
9da0fdce12 Revert r284545 again as the regression in ppc still exists. There is bug in MBPI exposed by th patch.
Also update the section.ll to fix non-x86 failure.

llvm-svn: 284563
2016-10-19 01:18:25 +00:00