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1366 Commits

Author SHA1 Message Date
Evan Cheng
fe745cba18 I can type. 
llvm-svn: 78453
 2009-08-08 02:54:37 +00:00
Chris Lattner
7bf6e40552 make printInstruction return void since its result is omitted. Make the 
error condition get trapped with an assert.

llvm-svn: 78449
 2009-08-08 01:32:19 +00:00
David Goodwin
c0fe95d8ce Make NEON single-precision FP support the default for cortex-a8 (again). 
llvm-svn: 78430
 2009-08-07 23:32:33 +00:00
Anton Korobeynikov
2dfb75ca36 Unbreak the stuff 
llvm-svn: 78425
 2009-08-07 22:51:13 +00:00
Anton Korobeynikov
9b52601704 2 more vdup.32 cases 
llvm-svn: 78419
 2009-08-07 22:36:50 +00:00
Evan Cheng
897663328b A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR. 
llvm-svn: 78418
 2009-08-07 22:36:37 +00:00
Evan Cheng
2bdb247c12 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng
7a2e5ba404 This is done. 
llvm-svn: 78399
 2009-08-07 19:34:52 +00:00
Evan Cheng
9c51e8f1fa Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode. 
llvm-svn: 78398
 2009-08-07 19:34:35 +00:00
Evan Cheng
0dab4cc8a0 Fix support to use NEON for single precision fp math. 
llvm-svn: 78397
 2009-08-07 19:30:41 +00:00
Evan Cheng
ece37695db Error out, rather than infinite looping, if constant island pass can't converge. 
llvm-svn: 78377
 2009-08-07 07:35:21 +00:00
Evan Cheng
5af3c8154b tBfar is bl, which clobbers LR. 
llvm-svn: 78370
 2009-08-07 05:45:07 +00:00
Dan Gohman
1c41d60c4a Fix a bunch of namespace pollution. 
llvm-svn: 78363
 2009-08-07 01:32:21 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations. 
llvm-svn: 78330
 2009-08-06 18:47:44 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Bob Wilson
905678ab37 Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
 2009-08-06 00:24:27 +00:00
Bob Wilson
6ee52e0047 Add a new pre-allocation pass to assign adjacent registers for Neon instructions 
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256
 2009-08-05 23:12:45 +00:00
David Goodwin
6e4065d7c6 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. 
llvm-svn: 78244
 2009-08-05 21:02:22 +00:00
Anton Korobeynikov
7a0835dec5 Remove redundand checks: the only way to have, e.g. f32 RegVT is exactly 
hardfloat case.

llvm-svn: 78237
 2009-08-05 20:15:19 +00:00
Anton Korobeynikov
7f9b6ff4a3 Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv. 
llvm-svn: 78232
 2009-08-05 19:40:16 +00:00
Anton Korobeynikov
07ce0611d9 Missed pieces for ARM HardFP ABI. 
Patch by Sandeep Patel!

llvm-svn: 78225
 2009-08-05 19:04:42 +00:00
Daniel Dunbar
3d2ac751da Remove some dead code. 
llvm-svn: 78219
 2009-08-05 18:12:37 +00:00
Bob Wilson
c0e1bed13f Remove a redundant declaration. 
llvm-svn: 78216
 2009-08-05 17:39:44 +00:00
David Goodwin
9013115518 Disable NEON single-precision FP support for Cortex-A8, for now... 
llvm-svn: 78209
 2009-08-05 16:40:57 +00:00
Devang Patel
fde898c9f1 Remove dead code. MDNode and MDString are not Constant anymore. 
llvm-svn: 78207
 2009-08-05 16:40:02 +00:00
David Goodwin
47064aa1c6 By default, for cortex-a8 use NEON for single-precision FP. 
llvm-svn: 78200
 2009-08-05 16:01:19 +00:00
Evan Cheng
a27fac5075 80 col violations. 
llvm-svn: 78175
 2009-08-05 06:41:25 +00:00
Bob Wilson
15c5c15ccb Oops. I didn't mean to commit this piece yet. 
llvm-svn: 78146
 2009-08-05 02:47:13 +00:00
Dan Gohman
5d566d918b Major calling convention code refactoring. 
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142
 2009-08-05 01:29:28 +00:00
Dan Gohman
4b2748d474 Don't flush the raw_ostream between each MachineFunction. These flush 
calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.

llvm-svn: 78137
 2009-08-05 00:49:25 +00:00
Bob Wilson
1fe51064ba Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136
 2009-08-05 00:49:09 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Bob Wilson
3607eeebfa Replace dregsingle operand modifier with explicit escaped curly brackets. 
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.

llvm-svn: 78109
 2009-08-04 21:39:33 +00:00
Evan Cheng
2ec9ab08d8 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
llvm-svn: 78104
 2009-08-04 21:12:13 +00:00
David Goodwin
648590849c Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
Evan Cheng
29fe8806d5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
llvm-svn: 78086
 2009-08-04 18:46:17 +00:00
David Goodwin
5efde448fa Match common pattern for FNMAC. Add NEON SP support. 
llvm-svn: 78085
 2009-08-04 18:44:29 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Anton Korobeynikov
10f01c8dd7 Ooops, I was too fast to commit the wrong fix :( 
llvm-svn: 78060
 2009-08-04 11:18:31 +00:00
Anton Korobeynikov
41ba9004b6 Fix a typo - this unbreaks llvm-gcc build on arm 
llvm-svn: 78059
 2009-08-04 11:12:51 +00:00
Evan Cheng
04035adc46 Thumb2 does not have ib (increment before) and da (decrement after) forms of ldm / stm. 
llvm-svn: 78057
 2009-08-04 08:34:18 +00:00
Evan Cheng
38da233adf Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. 
llvm-svn: 78032
 2009-08-04 01:56:09 +00:00
Evan Cheng
5711586a17 Load / store multiple pass fixes for Thumb2. Not enabled yet. 
llvm-svn: 78031
 2009-08-04 01:43:45 +00:00
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Bob Wilson
fe37bdfdd8 Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the 
results to fixed registers.

llvm-svn: 78025
 2009-08-04 00:36:16 +00:00
Bob Wilson
154afab758 Minor cleanup. No functional changes intended. 
llvm-svn: 78024
 2009-08-04 00:25:01 +00:00
Chris Lattner
5247ac71e5 use TLOF to compute the section for a function instead of 
replicating the logic manually.

llvm-svn: 78011
 2009-08-03 22:32:50 +00:00
Chris Lattner
7d2dd6deac convert macho stub emission to use SwitchToSection instead of 
textual sections.

llvm-svn: 78007
 2009-08-03 22:18:15 +00:00
Bob Wilson
eb3b616a7e Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.

llvm-svn: 77992
 2009-08-03 20:36:38 +00:00