..
AsmParser
[RISCV] Silence unused variable warning in Release builds. NFC.
2020-06-27 23:24:28 +02:00
Disassembler
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
MCTargetDesc
[RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter
2020-07-15 10:52:42 +01:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
CMakeLists.txt
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
LLVMBuild.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.h
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
RISCV.td
[RISCV] Add support for -mcpu option.
2020-07-20 15:38:39 +02:00
RISCVAsmPrinter.cpp
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallLowering.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVInstrFormats.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVInstrInfo.cpp
[RISCV] Indirect branch generation in position independent code
2020-08-20 14:32:36 +02:00
RISCVInstrInfo.h
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVInstrInfo.td
[RISCV] Indirect branch generation in position independent code
2020-08-20 14:32:36 +02:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-27 13:07:37 +02:00
RISCVInstrInfoC.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoF.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoV.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-27 13:07:37 +02:00
RISCVISelDAGToDAG.h
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-27 13:07:37 +02:00
RISCVISelLowering.cpp
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
2020-07-27 13:07:37 +02:00
RISCVISelLowering.h
[RISCV] Optimize multiplication by constant
2020-07-07 18:50:24 -07:00
RISCVLegalizerInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVMachineFunctionInfo.h
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp
RISCV: Don't store function in RISCVMachineFunctionInfo
2020-06-30 16:08:51 -04:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVSchedRocket32.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVSchedRocket64.td
[RISCV] Assemble/Disassemble v-ext instructions.
2020-06-28 00:54:07 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVSubtarget.h
[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive
2020-07-09 23:07:39 -07:00
RISCVSystemOperands.td
[RISCV] Add mcountinhibit CSR
2020-07-01 08:27:00 -07:00
RISCVTargetMachine.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVTargetMachine.h
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00
RISCVTargetTransformInfo.h
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00
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