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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
64 lines
5.0 KiB
LLVM
64 lines
5.0 KiB
LLVM
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s
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; PR5367
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define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind {
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entry:
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br i1 undef, label %return, label %bb
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bb: ; preds = %bb, %entry
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%0 = load float, float* undef, align 4 ; <float> [#uses=1]
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%1 = load float, float* null, align 4 ; <float> [#uses=1]
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%2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
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%3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
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%4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
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%5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4]
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%6 = fsub <4 x float> zeroinitializer, %3 ; <<4 x float>> [#uses=1]
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%7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=2]
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%8 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
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%9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=2]
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%10 = fmul <4 x float> %7, %9 ; <<4 x float>> [#uses=1]
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%11 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%12 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=2]
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%13 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%14 = fmul <4 x float> %11, %13 ; <<4 x float>> [#uses=1]
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%15 = fadd <4 x float> %10, %14 ; <<4 x float>> [#uses=1]
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%16 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
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%17 = fadd <4 x float> %15, zeroinitializer ; <<4 x float>> [#uses=1]
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%18 = shufflevector <4 x float> %17, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
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%19 = fmul <4 x float> %7, %16 ; <<4 x float>> [#uses=1]
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%20 = fadd <4 x float> %19, zeroinitializer ; <<4 x float>> [#uses=1]
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%21 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
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%22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%23 = fmul <4 x float> %22, %9 ; <<4 x float>> [#uses=1]
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%24 = fadd <4 x float> %20, %23 ; <<4 x float>> [#uses=1]
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%25 = shufflevector <4 x float> %18, <4 x float> %24, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> ; <<4 x float>> [#uses=1]
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%26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1]
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%27 = fmul <4 x float> %26, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
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%28 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %5 ; <<4 x float>> [#uses=1]
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%29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
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%30 = fmul <4 x float> zeroinitializer, %29 ; <<4 x float>> [#uses=1]
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%31 = fmul <4 x float> %30, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]
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%32 = shufflevector <4 x float> %27, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%33 = shufflevector <4 x float> %28, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
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%34 = shufflevector <2 x float> %33, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
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%35 = fmul <4 x float> %32, %34 ; <<4 x float>> [#uses=1]
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%36 = fadd <4 x float> %35, zeroinitializer ; <<4 x float>> [#uses=1]
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%37 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
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%38 = shufflevector <4 x float> %37, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
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%39 = fmul <4 x float> zeroinitializer, %38 ; <<4 x float>> [#uses=1]
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%40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1]
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%41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1]
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%42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
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%43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1]
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store float undef, float* undef, align 4
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store float 0.000000e+00, float* null, align 4
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%44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1]
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store float %44, float* undef, align 4
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br i1 undef, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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