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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
86 lines
1.9 KiB
LLVM
86 lines
1.9 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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@a = global i8 1, align 1
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@b = global i16 2, align 2
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define void @t1() nounwind uwtable ssp {
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; ARM: t1
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; ARM: ldrb
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; ARM-NOT: uxtb
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; ARM-NOT: and{{.*}}, #255
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; THUMB: t1
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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; THUMB-NOT: and{{.*}}, #255
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%1 = load i8, i8* @a, align 1
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call void @foo1(i8 zeroext %1)
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ret void
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}
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define void @t2() nounwind uwtable ssp {
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; ARM: t2
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t2
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16, i16* @b, align 2
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call void @foo2(i16 zeroext %1)
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ret void
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}
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declare void @foo1(i8 zeroext)
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declare void @foo2(i16 zeroext)
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define i32 @t3() nounwind uwtable ssp {
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; ARM: t3
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; ARM: ldrb
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; ARM-NOT: uxtb
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; ARM-NOT: and{{.*}}, #255
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; THUMB: t3
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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; THUMB-NOT: and{{.*}}, #255
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%1 = load i8, i8* @a, align 1
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%2 = zext i8 %1 to i32
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ret i32 %2
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}
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define i32 @t4() nounwind uwtable ssp {
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; ARM: t4
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t4
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16, i16* @b, align 2
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%2 = zext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t5() nounwind uwtable ssp {
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; ARM: t5
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; ARM: ldrsh
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; ARM-NOT: sxth
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; THUMB: t5
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; THUMB: ldrsh
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; THUMB-NOT: sxth
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%1 = load i16, i16* @b, align 2
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%2 = sext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t6() nounwind uwtable ssp {
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; ARM: t6
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; ARM: ldrsb
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; ARM-NOT: sxtb
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; THUMB: t6
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; THUMB: ldrsb
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; THUMB-NOT: sxtb
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%1 = load i8, i8* @a, align 2
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%2 = sext i8 %1 to i32
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ret i32 %2
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}
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