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82514bcbc5
This allows the optimization to rearrange loads and stores more aggressively. This doesn't really affect performance, but it helps codesize. Differential Revision: https://reviews.llvm.org/D30839 llvm-svn: 298021
41 lines
1.1 KiB
YAML
41 lines
1.1 KiB
YAML
# RUN: llc -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s
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--- |
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target triple = "thumbv7---eabi"
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define void @ldrd_strd_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) {
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entry:
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%0 = load i32, i32* %y, align 4
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store i32 %0, i32* %x, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1
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%1 = load i32, i32* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1
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store i32 %1, i32* %arrayidx3, align 4
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ret void
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}
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...
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---
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name: ldrd_strd_aa
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alignment: 1
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: %r0, %r1
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%1 : gpr = COPY %r1
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%0 : gpr = COPY %r0
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%2 : gpr = t2LDRi12 %1, 0, 14, _ :: (load 4 from %ir.y)
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t2STRi12 killed %2, %0, 0, 14, _ :: (store 4 into %ir.x)
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%3 : gpr = t2LDRi12 %1, 4, 14, _ :: (load 4 from %ir.arrayidx2)
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t2STRi12 killed %3, %0, 4, 14, _ :: (store 4 into %ir.arrayidx3)
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; CHECK: t2LDRi12
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; CHECK-NEXT: t2LDRi12
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; CHECK-NEXT: t2STRi12
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; CHECK-NEXT: t2STRi12
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tBX_RET 14, _
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...
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