mirror of
https://github.com/RPCS3/llvm-mirror.git
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0f6e617e90
This somehow got missed in the AArch64 merge, so should fix a performance regression since 3.4. llvm-svn: 210984
165 lines
5.4 KiB
LLVM
165 lines
5.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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; CHECK: autogen_SD19655
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; CHECK: scvtf
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; CHECK: ret
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define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
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%T = load <2 x i64>* %addr
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%F = sitofp <2 x i64> %T to <2 x float>
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store <2 x float> %F, <2 x float>* %addrfloat
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ret void
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}
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define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i32_to_v2f64:
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
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; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
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; CHECK-NEXT: ret
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%conv = sitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
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; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
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; CHECK-NEXT: ret
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%conv = uitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i16_to_v2f64:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: scvtf.2d v0, [[VAL64]]
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%conv = sitofp <2 x i16> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
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; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: ucvtf.2d v0, [[VAL64]]
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%conv = uitofp <2 x i16> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i8_to_v2f64:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: scvtf.2d v0, [[VAL64]]
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%conv = sitofp <2 x i8> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
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; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: ucvtf.2d v0, [[VAL64]]
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%conv = uitofp <2 x i8> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i64_to_v2f32:
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; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
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; CHECK: fcvtn v0.2s, [[VAL64]].2d
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%conv = sitofp <2 x i64> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i64_to_v2f32
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; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0
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; CHECK: fcvtn v0.2s, [[VAL64]].2d
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%conv = uitofp <2 x i64> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_signed_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i16_to_v2f32:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
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; CHECK: scvtf.2s v0, [[VAL32]]
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%conv = sitofp <2 x i16> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i16_to_v2f32
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; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ucvtf.2s v0, [[VAL32]]
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%conv = uitofp <2 x i16> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_signed_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i8_to_v2f32:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
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; CHECK: scvtf.2s v0, [[VAL32]]
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%conv = sitofp <2 x i8> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i8_to_v2f32
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; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ucvtf.2s v0, [[VAL32]]
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%conv = uitofp <2 x i8> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v4i16_to_v4f32:
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; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: scvtf.4s v0, [[VAL32]]
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%conv = sitofp <4 x i16> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
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; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: ucvtf.4s v0, [[VAL32]]
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%conv = uitofp <4 x i16> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v4i8_to_v4f32:
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; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
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; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
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; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
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; CHECK: scvtf.4s v0, [[VAL32]]
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%conv = sitofp <4 x i8> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
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; CHECK: bic.4h v0, #0xff, lsl #8
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; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: ucvtf.4s v0, [[VAL32]]
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%conv = uitofp <4 x i8> %v to <4 x float>
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ret <4 x float> %conv
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}
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