| .. |
|
AArch64
|
This patch eanble register coalescing to coalesce the following:
|
2015-07-23 19:24:53 +00:00 |
|
AMDGPU
|
AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
|
2015-07-20 14:28:41 +00:00 |
|
ARM
|
[ARM] Make the frame lowering code ready for shrink-wrapping.
|
2015-07-22 16:34:37 +00:00 |
|
BPF
|
[bpf] rename triple names bpf_be -> bpfeb
|
2015-06-05 16:11:14 +00:00 |
|
CPP
|
|
|
|
Generic
|
Targets: commonize some stack realignment code
|
2015-07-20 22:51:32 +00:00 |
|
Hexagon
|
[Hexagon] Generate MUX from conditional transfers when dot-new not possible
|
2015-07-20 21:23:25 +00:00 |
|
Inputs
|
|
|
|
Mips
|
[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)
|
2015-07-15 08:39:35 +00:00 |
|
MIR
|
MIR Serialization: Serialize the '.cfi_offset' CFI instruction.
|
2015-07-23 23:09:07 +00:00 |
|
MSP430
|
|
|
|
NVPTX
|
[BranchFolding] do not iterate the aliases of virtual registers
|
2015-07-22 04:16:52 +00:00 |
|
PowerPC
|
[PPC64LE] More vector swap optimization TLC
|
2015-07-21 21:40:17 +00:00 |
|
SPARC
|
[SPARC] Cleanup handling of the Y/ASR registers.
|
2015-07-08 16:25:12 +00:00 |
|
SystemZ
|
|
|
|
Thumb
|
[ARM] Make the frame lowering code ready for shrink-wrapping.
|
2015-07-22 16:34:37 +00:00 |
|
Thumb2
|
ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
|
2015-07-21 00:18:59 +00:00 |
|
WebAssembly
|
WebAssembly: test that valid -mcpu flags are accepted.
|
2015-07-23 23:00:04 +00:00 |
|
WinEH
|
[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name
|
2015-07-13 17:55:14 +00:00 |
|
X86
|
fix crash in machine trace metrics due to processing dbg_value instructions (PR24199)
|
2015-07-23 22:56:53 +00:00 |
|
XCore
|
Move the personality function from LandingPadInst to Function
|
2015-06-17 20:52:32 +00:00 |
