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f4e81c479c
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
96 lines
3.2 KiB
LLVM
96 lines
3.2 KiB
LLVM
; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
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; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
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; Cases where $rs > $rt can have the operands swapped as ==,!= are commutative.
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; Cases where beq & bne where $rs == $rt have to inhibited from being turned
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; into compact branches but arguably should not occur. This test covers the
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; $rs == $rt case.
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; Starting from dwarf exception handling preparation skips optimizations that
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; may simplify out the crucical bnec $4, $4 instruction.
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define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv:
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entry:
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%ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99
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br label %do.body121
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for.cond117:
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%alsr.iv.next = add nsw i32 %alsr.iv, -1
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%ascevgep340 = getelementptr i32, i32* %alsr.iv339, i64 -1
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%acmp118 = icmp sgt i32 %alsr.iv.next, 0
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br i1 %acmp118, label %do.body121, label %if.then143
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do.body121:
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%alsr.iv339 = phi i32* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
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%alsr.iv = phi i32 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
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%a9 = add i32 %alsr.iv, -1
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%alnot124 = icmp eq i32 %alsr.iv, %alsr.iv
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br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
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do.body134:
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%a10 = add i32 %alsr.iv, -1
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%a11 = load i32, i32* %alsr.iv339, align 4, !tbaa !5
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; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
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; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
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%alnot137 = icmp eq i32 %a9, %a11
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br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
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if.then143:
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ret void
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unreachable
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do.end146:
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%alnot151 = icmp eq i32 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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define internal void @_ZL14TestRemoveLastv64(i64* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv64:
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entry:
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%ascevgep = getelementptr i64, i64* %alist.sroa.0.4, i64 99
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br label %do.body121
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for.cond117:
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%alsr.iv.next = add nsw i64 %alsr.iv, -1
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%ascevgep340 = getelementptr i64, i64* %alsr.iv339, i64 -1
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%acmp118 = icmp sgt i64 %alsr.iv.next, 0
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br i1 %acmp118, label %do.body121, label %if.then143
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do.body121:
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%alsr.iv339 = phi i64* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
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%alsr.iv = phi i64 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
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%a9 = add i64 %alsr.iv, -1
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%alnot124 = icmp eq i64 %alsr.iv, %alsr.iv
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br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
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do.body134:
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%a10 = add i64 %alsr.iv, -1
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%a11 = load i64, i64* %alsr.iv339, align 4, !tbaa !5
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; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
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; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
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%alnot137 = icmp eq i64 %a9, %a11
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br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
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if.then143:
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ret void
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unreachable
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do.end146:
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%alnot151 = icmp eq i64 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"int", !3, i64 0}
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!11 = !{!"branch_weights", i32 2000, i32 1}
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!12 = !{!"branch_weights", i32 -388717296, i32 7818360}
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