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36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; RUN: llc -O2 -march=hexagon < %s
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; REQUIRES: asserts
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%0 = type { [2 x [8 x [16 x i8]]], [4 x [16 x %1*]] }
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%1 = type { i32, i32, i8, i8, %2, %6* }
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%2 = type { i32, i32, %3*, i8, i16, i16, i8 }
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%3 = type { i16, i16, %4, i16, i8, i16, %5, i32 }
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%4 = type { i32 }
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%5 = type { i16, i16 }
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%6 = type { %7* }
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%7 = type { [16 x i16], [16 x i16] }
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; Function Attrs: norecurse nounwind
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define void @f0(%0* nocapture %a0) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v6, %b1 ]
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%v1 = getelementptr inbounds %0, %0* %a0, i32 0, i32 1, i32 3, i32 %v0
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%v2 = bitcast %1** %v1 to i32*
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%v3 = load i32, i32* %v2, align 4
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store i32 %v3, i32* undef, align 4
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%v4 = getelementptr inbounds %0, %0* %a0, i32 0, i32 1, i32 0, i32 %v0
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%v5 = bitcast %1** %v4 to i32*
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store i32 %v3, i32* %v5, align 4
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%v6 = add nuw nsw i32 %v0, 1
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%v7 = icmp eq i32 %v6, 16
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br i1 %v7, label %b2, label %b1
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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