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llvm-mirror/test/CodeGen/Hexagon/vect/vect-vaddh.ll
Krzysztof Parzyszek 9cc7bfdeec [Hexagon] Add support for vector instructions
llvm-svn: 232728
2015-03-19 16:33:08 +00:00

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LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vaddh
define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind {
entry:
%0 = add <2 x i16> %a, %b
ret <2 x i16> %0
}