1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00
llvm-mirror/test/MachineVerifier
Matt Arsenault bb6d824b20 GlobalISel: Relax verification of physical register copy types
This was picking a concrete size for a physical register, and
enforcing exact match on the virtual register's type size. Some
targets add multiple types to a register class, and some are smaller
than the full bit width. For example x86 adds f32 to 128-bit xmm
registers, and AMDGPU adds i16/f16 to 32-bit registers.

It might be better to represent these cases as a copy of the full
register and an extraction of the subpart, but a lot of code assumes
you can directly copy. This will help fix the current usage of the DAG
calling convention infrastructure which is incompatible with how
GlobalISel is now using it.

The API is somewhat cumbersome here, but I just mirrored the existing
functions, except now with LLTs (and allow returning null on failure,
unlike the MVT version). I think the concept of selecting register
classes based on type is flawed to begin with, but I'm trying to keep
this compatible with the existing handling.
2021-04-28 08:45:41 -04:00
..
generic-vreg-undef-use.mir
live-ins-01.mir
live-ins-02.mir
live-ins-03.mir
test_copy_mismatch_types.mir
test_copy_physregs_x86.mir GlobalISel: Relax verification of physical register copy types 2021-04-28 08:45:41 -04:00
test_copy.mir
test_g_add.mir
test_g_addrspacecast.mir
test_g_assert_sext_register_bank_class.mir [GlobalISel] Add G_ASSERT_SEXT 2021-02-17 13:10:34 -08:00
test_g_assert_sext.mir [GlobalISel] Add G_ASSERT_SEXT 2021-02-17 13:10:34 -08:00
test_g_assert_zext_register_bank_class.mir
test_g_assert_zext.mir [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT 2021-02-12 21:33:27 +00:00
test_g_bitcast.mir
test_g_brindirect_is_indirect_branch.mir
test_g_brjt_is_indirect_branch.mir
test_g_brjt.mir
test_g_build_vector_trunc.mir
test_g_build_vector.mir
test_g_bzero.mir [AArch64][GlobalISel] Emit bzero on Darwin 2021-03-25 17:14:25 -07:00
test_g_concat_vectors.mir GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources 2021-03-01 09:10:36 -05:00
test_g_constant.mir
test_g_dyn_stackalloc.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_icmp.mir
test_g_insert.mir
test_g_intrinsic_w_side_effects.mir
test_g_intrinsic.mir
test_g_inttoptr.mir
test_g_jump_table.mir
test_g_load.mir
test_g_memcpy.mir
test_g_memset.mir
test_g_merge_values.mir
test_g_phi.mir
test_g_ptr_add.mir
test_g_ptrmask.mir
test_g_ptrtoint.mir
test_g_rotr_rotl.mir [GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates. 2021-03-25 17:23:30 -07:00
test_g_select.mir
test_g_sext_inreg.mir [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT 2021-02-12 21:33:27 +00:00
test_g_sextload.mir
test_g_shuffle_vector.mir
test_g_store.mir
test_g_trunc.mir
test_g_ubfx_sbfx.mir Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir 2021-03-24 11:23:08 -07:00
test_g_zextload.mir
test_phis_precede_nonphis.mir
test_vector_reductions.mir
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir
verifier-phi-fail0.mir
verifier-phi.mir
verifier-pseudo-terminators.mir
verifier-statepoint.mir
verify-regbankselected.mir
verify-regops.mir
verify-selected.mir