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4c52f7daa5
Kicks off the implementation of wasm SIMD128 support (spec: https://github.com/stoklund/portable-simd/blob/master/portable-simd.md), adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4. The spec is WIP, and might change in the near future. Patch by João Porto Differential Revision: https://reviews.llvm.org/D22686 llvm-svn: 277543
67 lines
2.5 KiB
TableGen
67 lines
2.5 KiB
TableGen
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This is a target description file for the WebAssembly architecture,
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/// which is also known as "wasm".
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// WebAssembly Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
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"Enable 128-bit SIMD">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "WebAssemblyRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrInfo.td"
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def WebAssemblyInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// WebAssembly Processors supported.
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//===----------------------------------------------------------------------===//
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// Minimal Viable Product.
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def : ProcessorModel<"mvp", NoSchedModel, []>;
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// Generic processor: latest stable version.
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def : ProcessorModel<"generic", NoSchedModel, []>;
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// Latest and greatest experimental version of WebAssembly. Bugs included!
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def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def WebAssembly : Target {
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let InstructionSet = WebAssemblyInstrInfo;
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}
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