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llvm-mirror/test/MC/Disassembler/PowerPC
Justin Hibbits 668c53374d Complete the SPE instruction set patterns
This is the lead-up to having SPE codegen.  Add the rest of the
instructions, along with MC tests.

Differential Revision:  https://reviews.llvm.org/D44829

llvm-svn: 337346
2018-07-18 04:24:57 +00:00
..
dcbt.txt
lit.local.cfg
ppc32-extpid-e500.txt PowerPC: support external pid instructions in MC layer. 2017-12-10 08:43:19 +00:00
ppc64-encoding-4xx.txt
ppc64-encoding-6xx.txt
ppc64-encoding-bookII.txt [PowerPC] Fix incorrectly encoded wait instruction 2018-06-25 19:28:27 +00:00
ppc64-encoding-bookIII.txt
ppc64-encoding-e500.txt Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
ppc64-encoding-ext.txt
ppc64-encoding-fp.txt
ppc64-encoding-p8vector.txt
ppc64-encoding-p9vector.txt
ppc64-encoding-vmx.txt
ppc64-encoding.txt [Power9] Add missing Power9 instructions. 2017-09-19 15:22:36 +00:00
ppc64-operands.txt
ppc64le-encoding.txt
qpx.txt
vsx.txt [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9. 2018-02-23 15:55:16 +00:00