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llvm-mirror/test/MC/Disassembler
Pablo Barrio 72d3164a16 [AArch64] Add command-line option for SSBS
Summary:
SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SSBS, as it was previously only possible to
enable by selecting -march=armv8.5-a.

Similar patch upstream in GNU binutils:
https://sourceware.org/ml/binutils/2018-09/msg00274.html

Reviewers: olista01, samparker, aemerson

Reviewed By: samparker

Subscribers: javed.absar, kristof.beyls, kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D54629

llvm-svn: 348137
2018-12-03 14:00:47 +00:00
..
AArch64 [AArch64] Add command-line option for SSBS 2018-12-03 14:00:47 +00:00
AMDGPU
ARC [ARC] Prevent InstPrinter from crashing on unknown condition codes. 2018-09-06 19:58:26 +00:00
ARM [ARM][v8.5A] Add speculation barriers SSBB and PSSBB 2018-09-28 08:27:56 +00:00
Hexagon
Lanai
Mips [mips] Add missing instructions 2018-08-29 11:35:03 +00:00
MSP430 [MSP430] Add MC layer 2018-11-15 12:29:43 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
RISCV [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988 2018-12-03 10:35:46 +00:00
Sparc
SystemZ
WebAssembly [WebAssembly] Read prefixed opcodes as ULEB128s 2018-11-09 01:57:00 +00:00
X86 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16. 2018-10-02 18:16:19 +00:00
XCore