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llvm-mirror/lib/MCA/HardwareUnits
Andrew Savonichev 064cc1a22c [MCA] Add support for in-order CPUs
This patch adds a pipeline to support in-order CPUs such as ARM
Cortex-A55.

In-order pipeline implements a simplified version of Dispatch,
Scheduler and Execute stages as a single stage. Entry and Retire
stages are common for both in-order and out-of-order pipelines.

Differential Revision: https://reviews.llvm.org/D94928
2021-03-04 14:08:19 +03:00
..
HardwareUnit.cpp
LSUnit.cpp
RegisterFile.cpp
ResourceManager.cpp
RetireControlUnit.cpp
Scheduler.cpp