Rosie Sumpter de55f5a044 [CostModel][AArch64] Improve cost model for vector reduction intrinsics ... OR, XOR and AND entries are added to the cost table. An extra cost is added when vector splitting occurs. This is done to address the issue of a missed SLP vectorization opportunity due to unreasonably high costs being attributed to the vector Or reduction (see: https://bugs.llvm.org/show_bug.cgi?id=44593). Differential Revision: https://reviews.llvm.org/D104538		2021-06-24 12:02:58 +01:00
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AArch64	[CostModel][AArch64] Improve cost model for vector reduction intrinsics	2021-06-24 12:02:58 +01:00
AMDGPU	[AMDGPU][CostModel] Refine cost model for control-flow instructions.	2021-04-10 09:20:24 +03:00
ARM	[InstructionCost] Don't conflate Invalid costs with Unknown costs.	2021-03-30 09:29:42 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
SystemZ	Revert "[NFC] remove explicit default value for strboolattr attribute in tests"	2021-05-24 19:43:40 +02:00
X86	[CostModel][X86] Improve AVX1/AVX2 truncation costs	2021-06-08 10:41:03 +01:00
free-intrinsics-datalayout.ll
free-intrinsics-no_info.ll
no_info.ll