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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00
llvm-mirror/lib/Target/RISCV
Matt Arsenault 0738f328d7 CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().

llvm-svn: 364191
2019-06-24 15:50:29 +00:00
..
AsmParser [RISCV] Allow parsing immediates that use tilde & exclaim 2019-06-19 10:27:24 +00:00
Disassembler Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
MCTargetDesc [RISCV] Simplify RISCVAsmBackend::writeNopData(). NFC 2019-06-15 06:14:15 +00:00
TargetInfo Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
Utils [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
CMakeLists.txt [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
LLVMBuild.txt [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCV.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCV.td [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
RISCVAsmPrinter.cpp Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
RISCVCallingConv.td [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVFrameLowering.cpp [RISCV] Add CFI directives for RISCV prologue/epilog. 2019-06-12 03:04:22 +00:00
RISCVFrameLowering.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVInstrFormats.td [RISCV] Implement pseudo instructions for load/store from a symbol address. 2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVInstrInfo.h Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
RISCVInstrInfo.td [RISCV] Support assembling TLS LA pseudo instructions 2019-05-23 14:46:27 +00:00
RISCVInstrInfoA.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVInstrInfoC.td [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
RISCVInstrInfoD.td [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
RISCVInstrInfoM.td [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M 2019-01-25 05:11:34 +00:00
RISCVISelDAGToDAG.cpp [RISCV][NFC] Add break to case statement in RISCVDAGToDAGISel::Select 2019-01-22 07:22:00 +00:00
RISCVISelLowering.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVISelLowering.h [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVMCInstLower.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMergeBaseOffset.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
RISCVRegisterInfo.cpp CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.td [RISCV] Allow fp as an alias of s0 2019-03-11 21:35:26 +00:00
RISCVSubtarget.cpp [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
RISCVSubtarget.h [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
RISCVSystemOperands.td [RISCV] Allow access to FP CSRs without F extension 2019-03-08 23:01:08 +00:00
RISCVTargetMachine.cpp [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCVTargetMachine.h [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
RISCVTargetTransformInfo.h [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00