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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
42 lines
1.1 KiB
YAML
42 lines
1.1 KiB
YAML
# RUN: llc -march=hexagon -mcpu=hexagonv60 -run-pass hexagon-packetizer %s -o - | FileCheck %s
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# Check that a store can be packetized with a load that happens later
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# if these instructions are not aliased (the load will actually execute
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# first).
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# CHECK-LABEL: name: danny
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# CHECK: BUNDLE
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---
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name: danny
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tracksRegLiveness: true
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stack:
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- { id: 0, type: default, size: 4, alignment: 4 }
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- { id: 1, type: default, size: 4, alignment: 4 }
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body: |
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bb.0:
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liveins: $r0
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S2_storeri_io $r29, 0, $r0 :: (store 4 into %stack.0)
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$r1 = L2_loadri_io $r29, 4 :: (load 4 from %stack.1)
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...
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# Check that a store cannot be packetized with a load that happens later
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# if these instructions are aliased.
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# CHECK-LABEL: name: sammy
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# CHECK-NOT: BUNDLE
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# CHECK: S2_storeri_io $r29, 0, $r0
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# CHECK: $r1 = L2_loadri_io $r29, 0
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---
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name: sammy
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tracksRegLiveness: true
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stack:
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- { id: 0, type: default, size: 4, alignment: 4 }
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body: |
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bb.0:
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liveins: $r0
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S2_storeri_io $r29, 0, $r0 :: (store 4 into %stack.0)
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$r1 = L2_loadri_io $r29, 0 :: (load 4 from %stack.0)
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...
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