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llvm-mirror/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll
Matthias Braun 699544cc62 ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.
This improves the logic in several ways and is a preparation for
followup patches:
- First perform an analysis and create a list of merge candidates, then
  transform. This simplifies the code in that you have don't have to
  care to much anymore that you may be holding iterators to
  MachineInstrs that get removed.
- Analyze/Transform basic blocks in reverse order. This allows to use
  LivePhysRegs to find free registers instead of the RegisterScavenger.
  The RegisterScavenger will become less precise in the future as it
  relies on the deprecated kill-flags.
- Return the newly created node in MergeOps so there's no need to look
  around in the schedule to find it.
- Rename some MBBI iterators to InsertBefore to make their role clear.
- General code cleanup.

Differential Revision: http://reviews.llvm.org/D10140

llvm-svn: 241920
2015-07-10 18:08:49 +00:00

26 lines
667 B
LLVM

;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
%struct4bytes = type { i32 }
%struct20bytes = type { i32, i32, i32, i32, i32 }
define void @foo(%struct4bytes* byval %p0, ; --> R0
%struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
) {
;CHECK: sub sp, sp, #16
;CHECK: push {r11, lr}
;CHECK: add r12, sp, #8
;CHECK: stm r12, {r0, r1, r2, r3}
;CHECK: add r0, sp, #12
;CHECK: bl useInt
;CHECK: pop {r11, lr}
;CHECK: add sp, sp, #16
%1 = ptrtoint %struct20bytes* %p1 to i32
tail call void @useInt(i32 %1)
ret void
}
declare void @useInt(i32)