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https://github.com/RPCS3/llvm-mirror.git
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b69b9d3362
This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
367 lines
10 KiB
LLVM
367 lines
10 KiB
LLVM
; RUN: llc < %s -mtriple=armv8-eabi -mattr=+fullfp16 | FileCheck %s
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; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 | FileCheck %s
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; TODO: we can't pass half-precision arguments as "half" types yet. We do
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; that for the time being by passing "float %f.coerce" and the necessary
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; bitconverts/truncates. In these tests we pass i16 and use 1 bitconvert, which
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; is the shortest way to get a half type. But when we can pass half types, we
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; want to use that here.
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define half @fp16_vminnm_o(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_o:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp olt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_o_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_o_rev:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ogt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_u(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_u:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ult half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_ule(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_ule:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ule half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vminnm_u_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_u_rev:
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; CHECK-NOT: vminnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ugt half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_o(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_o:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ogt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_oge(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_oge:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp oge half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_o_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_o_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp olt half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_ole_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_ole_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ole half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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define half @fp16_vmaxnm_u(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_u:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ugt half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_uge(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_uge:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp uge half %0, %1
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%cond = select i1 %cmp, half %0, half %1
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ret half %cond
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}
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define half @fp16_vmaxnm_u_rev(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_u_rev:
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; CHECK-NOT: vmaxnm.f16
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entry:
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%0 = bitcast i16 %a to half
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%1 = bitcast i16 %b to half
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%cmp = fcmp ult half %0, %1
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%cond = select i1 %cmp, half %1, half %0
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ret half %cond
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}
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; known non-NaNs
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define half @fp16_vminnm_NNNo(i16 signext %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp olt half %0, 12.
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%cond1 = select i1 %cmp1, half %0, half 12.
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%cmp2 = fcmp olt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vminnm_NNNo_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmin.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp ogt half %0, 56.
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%cond1 = select i1 %cmp1, half 56., half %0
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%cmp2 = fcmp ogt half 78., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 78.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ult half 12., %0
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%cond1 = select i1 %cmp1, half 12., half %0
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%cmp2 = fcmp ult half %cond1, 34.
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%cond2 = select i1 %cmp2, half %cond1, half 34.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNule(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNule:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmin.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ule half 34., %0
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%cond1 = select i1 %cmp1, half 34., half %0
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%cmp2 = fcmp ule half %cond1, 56.
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%cond2 = select i1 %cmp2, half %cond1, half 56.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu_rev(i16 signext %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmin.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ugt half 56., %0
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%cond1 = select i1 %cmp1, half %0, half 56.
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%cmp2 = fcmp ugt half %cond1, 78.
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%cond2 = select i1 %cmp2, half 78., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp ogt half %0, 12.
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%cond1 = select i1 %cmp1, half %0, half 12.
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%cmp2 = fcmp ogt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNoge(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNoge:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp oge half %0, 34.
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%cond1 = select i1 %cmp1, half %0, half 34.
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%cmp2 = fcmp oge half 56., %cond1
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%cond2 = select i1 %cmp2, half 56., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmax.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp olt half %0, 56.
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%cond1 = select i1 %cmp1, half 56., half %0
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%cmp2 = fcmp olt half 78., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 78.
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNole_rev(i16 signext %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vmax.f16 d0, d1, d0
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp ole half %0, 78.
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%cond1 = select i1 %cmp1, half 78., half %0
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%cmp2 = fcmp ole half 90., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 90.
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNu(i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_NNNu:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], #1.200000e+01
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp ugt half 12., %0
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%cond1 = select i1 %cmp1, half 12., half %0
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%cmp2 = fcmp ugt half %cond1, 34.
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%cond2 = select i1 %cmp2, half %cond1, half 34.
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNuge(i16 signext %b) {
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; CHECK-LABEL: fp16_vmaxnm_NNNuge:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S4:s[0-9]]], r{{.}}
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmaxnm.f16 s2, [[S4]], [[S2]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %b to half
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%cmp1 = fcmp uge half 34., %0
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%cond1 = select i1 %cmp1, half 34., half %0
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%cmp2 = fcmp uge half %cond1, 56.
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%cond2 = select i1 %cmp2, half %cond1, half 56.
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ret half %cond2
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}
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define half @fp16_vminmaxnm_neg0(i16 signext %a) {
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; CHECK-LABEL: fp16_vminmaxnm_neg0:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S2]], [[S0]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp olt half %0, -0.
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%cond1 = select i1 %cmp1, half %0, half -0.
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%cmp2 = fcmp ugt half %cond1, -0.
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%cond2 = select i1 %cmp2, half %cond1, half -0.
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ret half %cond2
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}
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define half @fp16_vminmaxnm_e_0(i16 signext %a) {
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; CHECK-LABEL: fp16_vminmaxnm_e_0:
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; CHECK: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S0:s[0-9]]], r{{.}}
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; CHECK: vmin.f16 d0, d0, d1
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; CHECK: vmaxnm.f16 s0, [[S0]], [[S2]]
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp nsz ole half 0., %0
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%cond1 = select i1 %cmp1, half 0., half %0
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%cmp2 = fcmp nsz uge half 0., %cond1
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%cond2 = select i1 %cmp2, half 0., half %cond1
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ret half %cond2
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}
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define half @fp16_vminmaxnm_e_neg0(i16 signext %a) {
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; CHECK-LABEL: fp16_vminmaxnm_e_neg0:
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; CHECK: vldr.16 [[S0:s[0-9]]], .LCPI{{.*}}
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; CHECK: vmov.f16 [[S2:s[0-9]]], r{{.}}
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; CHECK: vminnm.f16 s2, [[S2]], [[S0]]
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; CHECK: vmax.f16 d0, d1, d0
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entry:
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%0 = bitcast i16 %a to half
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%cmp1 = fcmp nsz ule half -0., %0
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%cond1 = select i1 %cmp1, half -0., half %0
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%cmp2 = fcmp nsz oge half -0., %cond1
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%cond2 = select i1 %cmp2, half -0., half %cond1
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ret half %cond2
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}
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