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48e4d991e8
The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
97 lines
2.6 KiB
LLVM
97 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
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; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
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define i64 @f0(i64 %A, i64 %B) {
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; CHECK-LE-LABEL: f0:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: lsrs r3, r3, #1
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; CHECK-LE-NEXT: rrx r2, r2
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; CHECK-LE-NEXT: subs r0, r0, r2
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; CHECK-LE-NEXT: sbc r1, r1, r3
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-BE-LABEL: f0:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: lsrs r2, r2, #1
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; CHECK-BE-NEXT: rrx r3, r3
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; CHECK-BE-NEXT: subs r1, r1, r3
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; CHECK-BE-NEXT: sbc r0, r0, r2
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; CHECK-BE-NEXT: mov pc, lr
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%tmp = bitcast i64 %A to i64
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%tmp2 = lshr i64 %B, 1
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%tmp3 = sub i64 %tmp, %tmp2
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ret i64 %tmp3
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}
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define i32 @f1(i64 %x, i64 %y) {
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; CHECK-LE-LABEL: f1:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: lsl r0, r0, r2
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; CHECK-LE-NEXT: subs r1, r2, #32
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; CHECK-LE-NEXT: movpl r0, #0
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-BE-LABEL: f1:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: lsl r0, r1, r3
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; CHECK-BE-NEXT: subs r1, r3, #32
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; CHECK-BE-NEXT: movpl r0, #0
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; CHECK-BE-NEXT: mov pc, lr
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%a = shl i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f2(i64 %x, i64 %y) {
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; CHECK-LE-LABEL: f2:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: rsb r3, r2, #32
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; CHECK-LE-NEXT: lsr r0, r0, r2
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; CHECK-LE-NEXT: subs r2, r2, #32
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; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-LE-NEXT: asrpl r0, r1, r2
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-BE-LABEL: f2:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: rsb r2, r3, #32
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; CHECK-BE-NEXT: lsr r1, r1, r3
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; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
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; CHECK-BE-NEXT: subs r2, r3, #32
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; CHECK-BE-NEXT: asrpl r1, r0, r2
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; CHECK-BE-NEXT: mov r0, r1
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; CHECK-BE-NEXT: mov pc, lr
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%a = ashr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f3(i64 %x, i64 %y) {
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; CHECK-LE-LABEL: f3:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: rsb r3, r2, #32
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; CHECK-LE-NEXT: lsr r0, r0, r2
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; CHECK-LE-NEXT: subs r2, r2, #32
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; CHECK-LE-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-LE-NEXT: lsrpl r0, r1, r2
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; CHECK-LE-NEXT: mov pc, lr
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;
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; CHECK-BE-LABEL: f3:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: rsb r2, r3, #32
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; CHECK-BE-NEXT: lsr r1, r1, r3
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; CHECK-BE-NEXT: orr r1, r1, r0, lsl r2
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; CHECK-BE-NEXT: subs r2, r3, #32
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; CHECK-BE-NEXT: lsrpl r1, r0, r2
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; CHECK-BE-NEXT: mov r0, r1
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; CHECK-BE-NEXT: mov pc, lr
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%a = lshr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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