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9cb186cbd7
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
222 lines
6.2 KiB
LLVM
222 lines
6.2 KiB
LLVM
; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1-m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NON-MVE
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define i64 @shift_left_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_left_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_llsl
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shl = shl i64 %x, %y
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ret i64 %shl
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}
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define i64 @shift_left_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_left_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsrs r2, r0, #29
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; CHECK-NON-MVE-NEXT: lsls r1, r1, #3
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; CHECK-NON-MVE-NEXT: adds r1, r1, r2
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; CHECK-NON-MVE-NEXT: lsls r0, r0, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 3
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ret i64 %shl
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}
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define i64 @shift_left_imm_big(i64 %x) {
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; CHECK-LABEL: shift_left_imm_big:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r1, r0, #16
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 48
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ret i64 %shl
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}
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define i64 @shift_left_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_left_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsll r0, r1, #32
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_left_imm_big2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r1, r0
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; CHECK-NON-MVE-NEXT: movs r0, #0
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 32
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ret i64 %shl
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}
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define i64 @shift_left_imm_big3(i64 %x) {
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; CHECK-LABEL: shift_left_imm_big3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r1, r0, #1
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl i64 %x, 33
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ret i64 %shl
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}
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define i64 @shift_right_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_right_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: rsbs r2, r2, #0
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; CHECK-MVE-NEXT: lsll r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_llsr
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shr = lshr i64 %x, %y
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ret i64 %shr
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}
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define i64 @shift_right_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_right_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
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; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
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; CHECK-NON-MVE-NEXT: adds r0, r0, r2
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; CHECK-NON-MVE-NEXT: lsrs r1, r1, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 3
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ret i64 %shr
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}
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define i64 @shift_right_imm_big(i64 %x) {
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; CHECK-LABEL: shift_right_imm_big:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r1, #16
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 48
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ret i64 %shr
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}
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define i64 @shift_right_imm_big2(i64 %x) {
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; CHECK-MVE-LABEL: shift_right_imm_big2:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: lsrl r0, r1, #32
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_right_imm_big2:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: movs r0, r1
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; CHECK-NON-MVE-NEXT: movs r1, #0
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 32
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ret i64 %shr
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}
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define i64 @shift_right_imm_big3(i64 %x) {
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; CHECK-LABEL: shift_right_imm_big3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r1, #1
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i64 %x, 33
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ret i64 %shr
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}
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define i64 @shift_arithmetic_right_reg(i64 %x, i64 %y) {
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; CHECK-MVE-LABEL: shift_arithmetic_right_reg:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: asrl r0, r1, r2
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_arithmetic_right_reg:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: .save {r7, lr}
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; CHECK-NON-MVE-NEXT: push {r7, lr}
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; CHECK-NON-MVE-NEXT: bl __aeabi_lasr
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; CHECK-NON-MVE-NEXT: pop {r7}
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; CHECK-NON-MVE-NEXT: pop {r2}
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; CHECK-NON-MVE-NEXT: bx r2
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entry:
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%shr = ashr i64 %x, %y
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ret i64 %shr
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}
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define i64 @shift_arithmetic_right_imm(i64 %x) {
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; CHECK-MVE-LABEL: shift_arithmetic_right_imm:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: asrl r0, r1, #3
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: shift_arithmetic_right_imm:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: lsls r2, r1, #29
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; CHECK-NON-MVE-NEXT: lsrs r0, r0, #3
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; CHECK-NON-MVE-NEXT: adds r0, r0, r2
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; CHECK-NON-MVE-NEXT: asrs r1, r1, #3
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%shr = ashr i64 %x, 3
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ret i64 %shr
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}
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%struct.bar = type { i16, i8, [5 x i8] }
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define arm_aapcs_vfpcc void @fn1(%struct.bar* nocapture %a) {
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; CHECK-MVE-LABEL: fn1:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: ldr r2, [r0, #4]
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; CHECK-MVE-NEXT: movs r1, #0
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; CHECK-MVE-NEXT: lsll r2, r1, #8
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; CHECK-MVE-NEXT: strb r1, [r0, #7]
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; CHECK-MVE-NEXT: str.w r2, [r0, #3]
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NON-MVE-LABEL: fn1:
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; CHECK-NON-MVE: @ %bb.0: @ %entry
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; CHECK-NON-MVE-NEXT: ldr r1, [r0, #4]
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; CHECK-NON-MVE-NEXT: lsls r2, r1, #8
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; CHECK-NON-MVE-NEXT: movs r3, #3
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; CHECK-NON-MVE-NEXT: str r2, [r0, r3]
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; CHECK-NON-MVE-NEXT: adds r0, r0, #3
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; CHECK-NON-MVE-NEXT: lsrs r1, r1, #24
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; CHECK-NON-MVE-NEXT: strb r1, [r0, #4]
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; CHECK-NON-MVE-NEXT: bx lr
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entry:
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%carey = getelementptr inbounds %struct.bar, %struct.bar* %a, i32 0, i32 2
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%0 = bitcast [5 x i8]* %carey to i40*
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%bf.load = load i40, i40* %0, align 1
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%bf.clear = and i40 %bf.load, -256
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store i40 %bf.clear, i40* %0, align 1
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ret void
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}
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