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llvm-mirror/test/CodeGen/MIR
History
Matt Arsenault e350c07050 AMDGPU: Serialize mode from MachineFunctionInfo 
llvm-svn: 365653
2019-07-10 16:09:26 +00:00
..
AArch64 Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
AMDGPU AMDGPU: Serialize mode from MachineFunctionInfo 2019-07-10 16:09:26 +00:00
ARM
Generic Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19 00:25:39 +00:00
Hexagon
Mips
NVPTX
PowerPC
WebAssembly
X86 [MachineFunction] Base support for call site info tracking 2019-06-27 07:48:06 +00:00
README

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.