mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
99 lines
3.8 KiB
YAML
99 lines
3.8 KiB
YAML
# RUN: llc -o - %s -start-after=if-converter | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "E-m:e-i64:64-n32:64"
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
|
|
%struct.rwlock_t.0.22.58.68.242.244 = type {}
|
|
|
|
@tasklist_lock = external global %struct.rwlock_t.0.22.58.68.242.244, align 1
|
|
|
|
; Function Attrs: nounwind
|
|
define void @mm_update_next_owner(i8** %p1, i32* %p2) #0 {
|
|
entry:
|
|
%0 = load i8*, i8** %p1, align 8
|
|
br i1 undef, label %do.body.92, label %for.body.21
|
|
|
|
for.body.21: ; preds = %entry
|
|
unreachable
|
|
|
|
do.body.92: ; preds = %entry
|
|
%usage = getelementptr inbounds i8, i8* %0, i64 -48
|
|
%counter.i = bitcast i8* %usage to i32*
|
|
%call95 = tail call signext i32 bitcast (i32 (...)* @__raw_read_unlock to i32 (%struct.rwlock_t.0.22.58.68.242.244*)*)(%struct.rwlock_t.0.22.58.68.242.244* nonnull @tasklist_lock) #1
|
|
store volatile i32 0, i32* %p2, align 4
|
|
tail call void asm sideeffect "#compiler barrier", "~{memory}"() #1
|
|
%1 = tail call i32 asm sideeffect "\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", "=&r,r,~{cc},~{xer},~{memory}"(i32* %counter.i) #1
|
|
%cmp.i = icmp eq i32 %1, 0
|
|
br i1 %cmp.i, label %if.then.i, label %put_task_struct.exit
|
|
|
|
if.then.i: ; preds = %do.body.92
|
|
unreachable
|
|
|
|
put_task_struct.exit: ; preds = %do.body.92
|
|
ret void
|
|
}
|
|
|
|
declare signext i32 @__raw_read_unlock(...)
|
|
|
|
attributes #0 = { nounwind "target-cpu"="pwr7" }
|
|
attributes #1 = { nounwind }
|
|
|
|
...
|
|
---
|
|
name: mm_update_next_owner
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x3' }
|
|
- { reg: '$x4' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 144
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: true
|
|
hasCalls: true
|
|
maxCallFrameSize: 112
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
fixedStack:
|
|
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
|
|
- { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x3, $x4, $x29, $x30, $x29, $x30
|
|
|
|
$x0 = MFLR8 implicit $lr8
|
|
STD $x0, 16, $x1
|
|
$x1 = STDU $x1, -144, $x1
|
|
STD killed $x29, 120, $x1 :: (store 8 into %fixed-stack.1)
|
|
STD killed $x30, 128, $x1 :: (store 8 into %fixed-stack.0, align 16)
|
|
$x30 = OR8 $x4, $x4
|
|
$x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
|
|
$x29 = ADDI8 killed $x3, -48
|
|
$x3 = ADDIStocHA $x2, @tasklist_lock
|
|
$x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
|
|
BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
|
|
$r3 = LI 0
|
|
STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2)
|
|
INLINEASM &"#compiler barrier", 25
|
|
INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
|
|
; CHECK-LABEL: @mm_update_next_owner
|
|
; CHECK-NOT: lwarx 29, 0, 29
|
|
; CHECK-NOT: stwcx. 29, 0, 29
|
|
$cr0 = CMPLWI killed $r3, 0
|
|
$x30 = LD 128, $x1 :: (load 8 from %fixed-stack.0, align 16)
|
|
$x29 = LD 120, $x1 :: (load 8 from %fixed-stack.1)
|
|
$x1 = ADDI8 $x1, 144
|
|
$x0 = LD 16, $x1
|
|
MTLR8 $x0, implicit-def $lr8
|
|
BLR8 implicit $lr8, implicit $rm
|
|
|
|
...
|