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0e9fc4420b
Summary:
Patch adds support for the following instructions:
* EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR
Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62387
llvm-svn: 361936
40 lines
1.4 KiB
ArmAsm
40 lines
1.4 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element width
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bcax z0.b, z0.b, z1.s, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bcax z0.b, z0.b, z1.s, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bcax z0.h, z0.h, z1.h, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bcax z0.h, z0.h, z1.h, z2.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bcax z0.d, z0.d, z1.s, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bcax z0.d, z0.d, z1.s, z2.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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bcax z0.d, z1.d, z2.d, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: bcax z0.d, z1.d, z2.d, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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bcax z0.d, z0.d, z1.d, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: bcax z0.d, z0.d, z1.d, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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