1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-18 18:42:46 +02:00
llvm-mirror/test/MC
Francesco Petrogalli 5f5352f7e7 [MC][SVE] Fix data operand for instruction alias of st1d.
The version of `st1d` that operates with vector plus immediate
addressing mode uses the alias `st1d { <Zn>.d }, <Pg>, [<Za>.d]` for
rendering `st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]`. The disassembler was
generating `<Zn>.s` instead of `<Zn>.d>`.

Differential Revision: https://reviews.llvm.org/D86633
2020-08-26 20:12:13 +00:00
..
AArch64 [MC][SVE] Fix data operand for instruction alias of st1d. 2020-08-26 20:12:13 +00:00
AMDGPU AMDGPU: Add @LINE to assembler error test checks 2020-07-14 18:37:50 -04:00
ARM [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM 2020-07-10 18:24:11 +01:00
AsmParser [MC/AsmParser] layout-interdependency.s depends on having a proper triple 2020-07-13 14:38:47 -07:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [MC] [COFF] Make sure that weak external symbols are undefined symbols 2020-07-27 13:10:48 +02:00
Disassembler [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM 2020-07-10 18:24:11 +01:00
ELF [MC] Support .reloc sym+constant, *, * 2020-07-14 13:44:00 -07:00
Hexagon [Hexagon] pX.new cannot be used with p3:0 as producer 2020-05-19 17:06:34 -05:00
Lanai [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
MachO split darwin-version-min-load-command.s into Arm64 subtest to avoid failures 2020-06-30 14:49:04 -07:00
Mips [MC] Support .reloc sym+constant, *, * 2020-07-14 13:44:00 -07:00
MSP430 [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
PowerPC [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost VSX Vector 2020-07-09 17:06:03 -05:00
RISCV [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive 2020-07-09 23:07:39 -07:00
Sparc [Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names 2020-03-16 07:42:04 -07:00
SystemZ [SystemZ] Allow specifying integer registers as part of the address calculation 2020-07-08 18:20:24 +02:00
VE [VE] Support symbol with offset in assembly 2020-07-07 04:16:51 +09:00
WebAssembly [WebAssembly] Added 64-bit memory.grow/size/copy/fill 2020-07-06 12:49:50 -07:00
X86 [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register. 2020-07-20 15:44:42 +02:00