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9238097638
Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
36 lines
1.3 KiB
ArmAsm
36 lines
1.3 KiB
ArmAsm
// TRBE System registers
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//
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// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
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// Read from system register
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mrs x0, TRBLIMITR_EL1
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mrs x0, TRBPTR_EL1
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mrs x0, TRBBASER_EL1
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mrs x0, TRBSR_EL1
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mrs x0, TRBMAR_EL1
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mrs x0, TRBTRG_EL1
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mrs x0, TRBIDR_EL1
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// CHECK: mrs x0, TRBLIMITR_EL1 // encoding: [0x00,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBPTR_EL1 // encoding: [0x20,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBBASER_EL1 // encoding: [0x40,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBSR_EL1 // encoding: [0x60,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBMAR_EL1 // encoding: [0x80,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBTRG_EL1 // encoding: [0xc0,0x9b,0x38,0xd5]
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// CHECK: mrs x0, TRBIDR_EL1 // encoding: [0xe0,0x9b,0x38,0xd5]
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// Write to system register
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msr TRBLIMITR_EL1, x0
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msr TRBPTR_EL1, x0
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msr TRBBASER_EL1, x0
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msr TRBSR_EL1, x0
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msr TRBMAR_EL1, x0
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msr TRBTRG_EL1, x0
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// CHECK: msr TRBLIMITR_EL1, x0 // encoding: [0x00,0x9b,0x18,0xd5]
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// CHECK: msr TRBPTR_EL1, x0 // encoding: [0x20,0x9b,0x18,0xd5]
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// CHECK: msr TRBBASER_EL1, x0 // encoding: [0x40,0x9b,0x18,0xd5]
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// CHECK: msr TRBSR_EL1, x0 // encoding: [0x60,0x9b,0x18,0xd5]
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// CHECK: msr TRBMAR_EL1, x0 // encoding: [0x80,0x9b,0x18,0xd5]
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// CHECK: msr TRBTRG_EL1, x0 // encoding: [0xc0,0x9b,0x18,0xd5]
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