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5892dcede7
When these tests were originally written, the middle end would introduce an unnecessary copy from r24:r23->GPR16->r24:r23, and these tests mistakenly relied on it. The most optimal codegen for the functions in the test cases before this patch would be NOPs. This is because the first i16 argument always gets the same register allocation as an i16 return value in the AVR calling convention. These tests broke in r362963 when the codegen was improved and the redundant copy was eliminated. After this, the test functions were lowered to their optimal form - a 'ret' and nothing else. This patch prepends an extra i16 operand to each of the test functions so that a 16-bit copy must be inserted for the program to be correct. llvm-svn: 363131
9 lines
221 B
LLVM
9 lines
221 B
LLVM
; RUN: llc -mattr=avr25 -O0 < %s -march=avr | FileCheck %s
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; On most cores, the 16-bit 'MOVW' instruction can be used
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define i16 @reg_copy16(i16, i16 %a) {
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; CHECK-LABEL: reg_copy16
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; CHECK: movw r24, r22
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ret i16 %a
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}
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