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llvm-mirror/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
Matt Arsenault cc12b285b6 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00

48 lines
2.4 KiB
LLVM

; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \
; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | \
; RUN: FileCheck %s
define void @caller() {
entry:
%call = tail call <4 x i32> (double, double, double, ...) @split_spill(double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, <4 x i32> <i32 1, i32 2, i32 3, i32 4>)
ret void
}
declare <4 x i32> @split_spill(double, double, double, ...)
; CHECK: ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1
; CHECK: [[VECCONSTADDR:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load (s32) from got)
; CHECK: [[VECCONST:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[VECCONSTADDR]] :: (load (s128) from constant-pool)
; CHECK: [[STACKOFFSET:%[0-9]+]]:gprc = LI 48
; CHECK: STXVW4X killed [[VECCONST]], $r1, killed [[STACKOFFSET]] :: (store (s128))
; CHECK-DAG: [[ELEMENT1:%[0-9]+]]:gprc = LWZ 48, $r1 :: (load (s32))
; CHECK-DAG: [[ELEMENT2:%[0-9]+]]:gprc = LWZ 52, $r1 :: (load (s32))
; CHECK: [[FLOAT1ADDR:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.1, $r2 :: (load (s32) from got)
; CHECK: [[FLOAT1:%[0-9]+]]:f4rc = LFS 0, killed [[FLOAT1ADDR]] :: (load (s32) from constant-pool)
; CHECK: [[DOUBLE1:%[0-9]+]]:f8rc = COPY [[FLOAT1]]
; CHECK: [[FLOAT2ADDR:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.2, $r2 :: (load (s32) from got)
; CHECK: [[FLOAT2:%[0-9]+]]:f4rc = LFS 0, killed [[FLOAT2ADDR]] :: (load (s32) from constant-pool)
; CHECK: [[DOUBLE2:%[0-9]+]]:f8rc = COPY [[FLOAT2]]
; CHECK: [[DZERO:%[0-9]+]]:vsfrc = XXLXORdpz
; CHECK: [[DTOI1:%[0-9]+]]:gprc = LIS 16368
; CHECK: [[DTOI2:%[0-9]+]]:gprc = LIS 16384
; CHECK: [[IZERO:%[0-9]+]]:gprc = LI 0
; CHECK-DAG: $f1 = COPY [[DZERO]]
; CHECK-DAG: $r3 = COPY [[IZERO]]
; CHECK-DAG: $r4 = COPY [[IZERO]]
; CHECK-DAG: $f2 = COPY [[DOUBLE1]]
; CHECK-DAG: $r5 = COPY [[DTOI1]]
; CHECK-DAG: $r6 = COPY [[IZERO]]
; CHECK-DAG: $f3 = COPY [[DOUBLE2]]
; CHECK-DAG: $r7 = COPY [[DTOI2]]
; CHECK-DAG: $r8 = COPY [[IZERO]]
; CHECK-DAG: $r9 = COPY [[ELEMENT1]]
; CHECK-DAG: $r10 = COPY [[ELEMENT2]]
; CHECK: BL_NOP <mcsymbol .split_spill[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r3, implicit $r4, implicit $f2, implicit $r5, implicit $r6, implicit $f3, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def $v2