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0b832ca92a
As part of the effort to improve AIX support, regression test coverage misses quite a lot for AIX subtarget. This patch adds AIX triple to those don't need extra change, and we can cover more cases in following commits. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D94159
81 lines
1.8 KiB
LLVM
81 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s
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; mask 0xFFFFFFFE
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define i32 @test1(i32 %a) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 0, 0, 30
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; CHECK-NEXT: blr
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%and = and i32 %a, -2
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ret i32 %and
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}
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; mask 0xFFFFFFFFFFFFFFF9
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define i64 @test2(i64 %a) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 61, 2
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; CHECK-NEXT: rotldi 3, 3, 3
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; CHECK-NEXT: blr
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%and = and i64 %a, -7
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ret i64 %and
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}
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; mask: 0xFFFFFFC00000
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define i64 @test3(i64 %a) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 42, 22
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; CHECK-NEXT: rldicl 3, 3, 22, 16
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; CHECK-NEXT: blr
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%and = and i64 %a, 281474972516352
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ret i64 %and
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}
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; mask: 0xC000000FF
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define i64 @test4(i64 %a) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 30, 26
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; CHECK-NEXT: rldicl 3, 3, 34, 28
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; CHECK-NEXT: blr
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%and = and i64 %a, 51539607807
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ret i64 %and
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}
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; mask: 0xFFC0FFFF
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define i64 @test5(i64 %a) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 42, 6
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; CHECK-NEXT: rldicl 3, 3, 22, 32
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; CHECK-NEXT: blr
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%and = and i64 %a, 4290838527
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ret i64 %and
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}
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; mask: 0x3FC0FFE0
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define i64 @test6(i64 %a) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 4, 16320
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; CHECK-NEXT: ori 4, 4, 65504
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: blr
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%and = and i64 %a, 1069613024
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ret i64 %and
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}
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; mask: 0x3FC000001FFFF
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define i64 @test7(i64 %a) {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 22, 25
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; CHECK-NEXT: rldicl 3, 3, 42, 14
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; CHECK-NEXT: blr
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%and = and i64 %a, 1121501860462591
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ret i64 %and
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}
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