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11ea47a03f
The combine was disabled in 4e22c7265d86 as it caused failures in the ppc64be-multistage (bootstrap) bot. It turns out that the combine did not correctly update the MMO for the high load which caused aliased stores to be reported as unaliased. This patch fixes that problem and re-enables the combine.
176 lines
5.0 KiB
LLVM
176 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=ppc32 | FileCheck %s --check-prefixes=X32
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=pwr7 | FileCheck %s --check-prefixes=X32,PWR7_32
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=ppc64 | FileCheck %s --check-prefixes=X64
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=powerpc64-- -mcpu=pwr7 | FileCheck %s --check-prefixes=PWR7_64
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define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
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; X32-LABEL: STWBRX:
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; X32: # %bb.0:
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; X32-NEXT: stwbrx r3, r4, r5
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; X32-NEXT: blr
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;
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; X64-LABEL: STWBRX:
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; X64: # %bb.0:
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; X64-NEXT: extsw r5, r5
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; X64-NEXT: stwbrx r3, r4, r5
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: STWBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: extsw r5, r5
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; PWR7_64-NEXT: stwbrx r3, r4, r5
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i32 %off
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%tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*
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%tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )
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store i32 %tmp13, i32* %tmp1.upgrd.1
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ret void
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}
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define i32 @LWBRX(i8* %ptr, i32 %off) {
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; X32-LABEL: LWBRX:
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; X32: # %bb.0:
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; X32-NEXT: lwbrx r3, r3, r4
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; X32-NEXT: blr
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;
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; X64-LABEL: LWBRX:
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; X64: # %bb.0:
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; X64-NEXT: extsw r4, r4
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; X64-NEXT: lwbrx r3, r3, r4
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: LWBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: extsw r4, r4
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; PWR7_64-NEXT: lwbrx r3, r3, r4
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i32 %off
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%tmp1.upgrd.2 = bitcast i8* %tmp1 to i32*
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%tmp = load i32, i32* %tmp1.upgrd.2
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%tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp )
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ret i32 %tmp14
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}
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define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
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; X32-LABEL: STHBRX:
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; X32: # %bb.0:
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; X32-NEXT: sthbrx r3, r4, r5
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; X32-NEXT: blr
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;
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; X64-LABEL: STHBRX:
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; X64: # %bb.0:
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; X64-NEXT: extsw r5, r5
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; X64-NEXT: sthbrx r3, r4, r5
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: STHBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: extsw r5, r5
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; PWR7_64-NEXT: sthbrx r3, r4, r5
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i32 %off
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%tmp1.upgrd.3 = bitcast i8* %tmp1 to i16*
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%tmp5 = call i16 @llvm.bswap.i16( i16 %s )
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store i16 %tmp5, i16* %tmp1.upgrd.3
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ret void
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}
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define i16 @LHBRX(i8* %ptr, i32 %off) {
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; X32-LABEL: LHBRX:
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; X32: # %bb.0:
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; X32-NEXT: lhbrx r3, r3, r4
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; X32-NEXT: blr
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;
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; X64-LABEL: LHBRX:
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; X64: # %bb.0:
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; X64-NEXT: extsw r4, r4
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; X64-NEXT: lhbrx r3, r3, r4
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: LHBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: extsw r4, r4
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; PWR7_64-NEXT: lhbrx r3, r3, r4
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i32 %off
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%tmp1.upgrd.4 = bitcast i8* %tmp1 to i16*
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%tmp = load i16, i16* %tmp1.upgrd.4
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%tmp6 = call i16 @llvm.bswap.i16( i16 %tmp )
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ret i16 %tmp6
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}
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; TODO: combine the bswap feeding a store on subtargets
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; that do not have an STDBRX.
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define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
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; PWR7_32-LABEL: STDBRX:
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; PWR7_32: # %bb.0:
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; PWR7_32-NEXT: li r6, 4
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; PWR7_32-NEXT: add r7, r5, r8
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; PWR7_32-NEXT: stwbrx r4, r5, r8
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; PWR7_32-NEXT: stwbrx r3, r7, r6
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; PWR7_32-NEXT: blr
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;
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; X64-LABEL: STDBRX:
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; X64: # %bb.0:
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; X64-NEXT: rotldi r6, r3, 16
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; X64-NEXT: rotldi r7, r3, 8
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; X64-NEXT: rldimi r7, r6, 8, 48
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; X64-NEXT: rotldi r6, r3, 24
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; X64-NEXT: rldimi r7, r6, 16, 40
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; X64-NEXT: rotldi r6, r3, 32
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; X64-NEXT: rldimi r7, r6, 24, 32
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; X64-NEXT: rotldi r6, r3, 48
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; X64-NEXT: rldimi r7, r6, 40, 16
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; X64-NEXT: rotldi r6, r3, 56
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; X64-NEXT: rldimi r7, r6, 48, 8
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; X64-NEXT: rldimi r7, r3, 56, 0
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; X64-NEXT: stdx r7, r4, r5
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: STDBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: stdbrx r3, r4, r5
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i64 %off
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%tmp1.upgrd.1 = bitcast i8* %tmp1 to i64*
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%tmp13 = tail call i64 @llvm.bswap.i64( i64 %i )
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store i64 %tmp13, i64* %tmp1.upgrd.1
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ret void
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}
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define i64 @LDBRX(i8* %ptr, i64 %off) {
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; PWR7_32-LABEL: LDBRX:
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; PWR7_32: # %bb.0:
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; PWR7_32-NEXT: li r5, 4
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; PWR7_32-NEXT: add r7, r3, r6
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; PWR7_32-NEXT: lwbrx r4, r3, r6
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; PWR7_32-NEXT: lwbrx r3, r7, r5
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; PWR7_32-NEXT: blr
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;
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; X64-LABEL: LDBRX:
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; X64: # %bb.0:
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; X64-NEXT: li r6, 4
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; X64-NEXT: lwbrx r5, r3, r4
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; X64-NEXT: add r3, r3, r4
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; X64-NEXT: lwbrx r3, r3, r6
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; X64-NEXT: rldimi r5, r3, 32, 0
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; X64-NEXT: mr r3, r5
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; X64-NEXT: blr
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;
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; PWR7_64-LABEL: LDBRX:
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; PWR7_64: # %bb.0:
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; PWR7_64-NEXT: ldbrx r3, r3, r4
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; PWR7_64-NEXT: blr
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%tmp1 = getelementptr i8, i8* %ptr, i64 %off
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%tmp1.upgrd.2 = bitcast i8* %tmp1 to i64*
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%tmp = load i64, i64* %tmp1.upgrd.2
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%tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp )
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ret i64 %tmp14
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}
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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declare i64 @llvm.bswap.i64(i64)
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