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llvm-mirror/test/CodeGen/PowerPC/fdiv.ll
Jinsong Ji 4d8c0e830b [DAGCombine] reassoc flag shouldn't enable contract
According to IR LangRef, the FMF flag:

contract
Allow floating-point contraction (e.g. fusing a multiply followed by an
addition into a fused multiply-and-add).

reassoc
Allow reassociation transformations for floating-point instructions.
This may dramatically change results in floating-point.

My understanding is that these two flags shouldn't imply each other,
as we might have a SDNode that can be reassociated with others, but
not contractble.

eg: We may want following fmul/fad/fsub to freely reassoc, but don't
want fma being generated here.

   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc double %H, %E         ; <double> [#uses=1]

Before https://reviews.llvm.org/D45710, `reassoc` flag actually
did not imply isContratable either.

The current implementation also only check the flag in fadd node,
ignoring fmul node, this patch update that as well.

Reviewed By: spatel, qiucf

Differential Revision: https://reviews.llvm.org/D104247
2021-06-21 21:15:43 +00:00

26 lines
903 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi | FileCheck %s
define dso_local float @foo_nosw(float %0, float %1) local_unnamed_addr {
; CHECK-LABEL: foo_nosw:
; CHECK: # %bb.0:
; CHECK-NEXT: xsdivsp 1, 1, 2
; CHECK-NEXT: blr
%3 = fdiv contract reassoc arcp nsz float %0, %1
ret float %3
}
define dso_local float @foo(float %0, float %1) local_unnamed_addr {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: xsresp 3, 2
; CHECK-NEXT: xsmulsp 0, 1, 3
; CHECK-NEXT: xsnmsubasp 1, 2, 0
; CHECK-NEXT: xsmaddasp 0, 3, 1
; CHECK-NEXT: fmr 1, 0
; CHECK-NEXT: blr
%3 = fdiv contract reassoc arcp nsz ninf float %0, %1
ret float %3
}