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a779ff600d
In lowering of FLT_ROUNDS_, FPSCR content will be moved into FP register and then GPR, and then truncated into word. For subtargets without direct move support, it will store and then load. The load address needs adjustment (+4) only on big-endian targets. This patch fixes it on using generic opcodes on little-endian and subtargets with direct-move. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D91845
81 lines
2.4 KiB
LLVM
81 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s \
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; RUN: -check-prefix=PPC32
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64 | FileCheck %s \
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; RUN: -check-prefix=PPC64
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le -mattr=-direct-move \
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; RUN: | FileCheck %s -check-prefix=PPC64LE
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le | FileCheck %s \
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; RUN: -check-prefix=DM
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define i32 @foo() {
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; PPC32-LABEL: foo:
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; PPC32: # %bb.0: # %entry
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; PPC32-NEXT: stwu 1, -32(1)
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; PPC32-NEXT: .cfi_def_cfa_offset 32
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; PPC32-NEXT: mffs 0
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; PPC32-NEXT: stfd 0, 16(1)
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; PPC32-NEXT: lwz 3, 20(1)
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; PPC32-NEXT: clrlwi 4, 3, 30
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; PPC32-NEXT: not 3, 3
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; PPC32-NEXT: rlwinm 3, 3, 31, 31, 31
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; PPC32-NEXT: xor 3, 4, 3
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; PPC32-NEXT: stw 3, 24(1)
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; PPC32-NEXT: stw 3, 28(1)
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; PPC32-NEXT: addi 1, 1, 32
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: foo:
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; PPC64: # %bb.0: # %entry
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; PPC64-NEXT: mffs 0
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; PPC64-NEXT: stfd 0, -16(1)
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; PPC64-NEXT: lwz 3, -12(1)
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; PPC64-NEXT: clrlwi 4, 3, 30
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; PPC64-NEXT: not 3, 3
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; PPC64-NEXT: rlwinm 3, 3, 31, 31, 31
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; PPC64-NEXT: xor 3, 4, 3
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; PPC64-NEXT: stw 3, -8(1)
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; PPC64-NEXT: stw 3, -4(1)
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; PPC64-NEXT: blr
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;
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; PPC64LE-LABEL: foo:
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; PPC64LE: # %bb.0: # %entry
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; PPC64LE-NEXT: mffs 0
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; PPC64LE-NEXT: stfd 0, -16(1)
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; PPC64LE-NEXT: lwz 3, -16(1)
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; PPC64LE-NEXT: not 4, 3
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; PPC64LE-NEXT: clrlwi 3, 3, 30
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; PPC64LE-NEXT: rlwinm 4, 4, 31, 31, 31
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; PPC64LE-NEXT: xor 3, 3, 4
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; PPC64LE-NEXT: stw 3, -8(1)
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; PPC64LE-NEXT: stw 3, -4(1)
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; PPC64LE-NEXT: blr
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;
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; DM-LABEL: foo:
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; DM: # %bb.0: # %entry
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; DM-NEXT: mffs 0
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; DM-NEXT: mffprd 3, 0
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; DM-NEXT: not 4, 3
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; DM-NEXT: clrlwi 3, 3, 30
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; DM-NEXT: rlwinm 4, 4, 31, 31, 31
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; DM-NEXT: xor 3, 3, 4
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; DM-NEXT: stw 3, -8(1)
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; DM-NEXT: stw 3, -4(1)
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; DM-NEXT: blr
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entry:
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%retval = alloca i32 ; <i32*> [#uses=2]
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%tmp = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%tmp1 = call i32 @llvm.flt.rounds( ) ; <i32> [#uses=1]
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store i32 %tmp1, i32* %tmp, align 4
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%tmp2 = load i32, i32* %tmp, align 4 ; <i32> [#uses=1]
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store i32 %tmp2, i32* %retval, align 4
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br label %return
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return: ; preds = %entry
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%retval3 = load i32, i32* %retval ; <i32> [#uses=1]
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ret i32 %retval3
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}
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declare i32 @llvm.flt.rounds() nounwind
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