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1b514619dd
* The method getRegAllocationHints() is now of bool type instead of void. If true is returned, regalloc (AllocationOrder) will *only* try to allocate the hints, as opposed to merely trying them before non-hinted registers. * TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with an increase in number of LOCRs. In this case, it is desired to force the hints even though there is a slight increase in spilling, because if a non-hinted register would be allocated, the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR (Load On Condition) SystemZ instruction must have both operands in either the low or high part of the 64 bit register. Reviewers: Quentin Colombet and Ulrich Weigand https://reviews.llvm.org/D36795 llvm-svn: 317879
76 lines
1.9 KiB
YAML
76 lines
1.9 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=greedy %s -o - \
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# RUN: | FileCheck %s
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#
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# Test that regalloc manages (via regalloc hints) to avoid a LOCRMux jump
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# sequence expansion.
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--- |
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declare i8* @foo(i8*, i32 signext, i32 signext) local_unnamed_addr
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define i8* @fun(i8* returned) {
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br label %2
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; <label>:2: ; preds = %6, %1
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%3 = zext i16 undef to i32
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switch i32 %3, label %4 [
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i32 15, label %6
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i32 125, label %5
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]
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; <label>:4: ; preds = %2
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br label %6
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; <label>:5: ; preds = %2
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br label %6
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; <label>:6: ; preds = %5, %4, %2
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%7 = phi i32 [ 4, %2 ], [ undef, %4 ], [ 10, %5 ]
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%8 = call i8* @foo(i8* undef, i32 signext undef, i32 signext %7)
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br label %2
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}
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...
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# CHECK: locr
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# CHECK-NOT: risblg
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---
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name: fun
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32bit }
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- { id: 1, class: gr64bit }
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- { id: 2, class: grx32bit }
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- { id: 3, class: grx32bit }
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- { id: 4, class: grx32bit }
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- { id: 5, class: grx32bit }
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- { id: 6, class: grx32bit }
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- { id: 7, class: gr64bit }
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- { id: 8, class: gr64bit }
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- { id: 9, class: gr64bit }
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- { id: 10, class: gr64bit }
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- { id: 11, class: gr32bit }
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frameInfo:
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hasCalls: true
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body: |
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bb.0 (%ir-block.1):
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%3 = LHIMux 0
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%2 = LHIMux 4
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%5 = LHIMux 10
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bb.1 (%ir-block.2):
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CHIMux %3, 0, implicit-def %cc
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%0 = LOCRMux undef %0, %5, 14, 6, implicit %cc
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%0 = LOCRMux %0, %2, 14, 6, implicit killed %cc
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ADJCALLSTACKDOWN 0, 0
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%7 = LGFR %0
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%r3d = LGHI 0
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%r4d = COPY %7
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CallBRASL @foo, undef %r2d, killed %r3d, killed %r4d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def dead %r2d
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ADJCALLSTACKUP 0, 0
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J %bb.1
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...
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