Kalle Raiskila 5e3c80d1f8 Add the check to the testcase of r106419. ... llvm-svn: 106421		2010-06-21 15:11:51 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
2010-04-07-DbgValueOtherTargets.ll	Split big test into multiple directories to cater to	2010-04-07 20:43:35 +00:00
and_ops.ll
bigstack.ll
bss.ll	Make sure this test tests something.	2010-04-09 19:03:31 +00:00
call_indirect.ll	Mark the SPU 'lr' instruction to never have side effects.	2010-06-21 15:08:16 +00:00
call.ll	Mark the SPU 'lr' instruction to never have side effects.	2010-06-21 15:08:16 +00:00
crash.ll	teach cellspu how to return i8 and i16 from calls,	2010-04-20 05:36:09 +00:00
ctpop.ll
dg.exp
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp32.ll
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll	Mark the SPU 'lr' instruction to never have side effects.	2010-06-21 15:08:16 +00:00
loads.ll	Mark the SPU 'lr' instruction to never have side effects.	2010-06-21 15:08:16 +00:00
mul_ops.ll
mul-with-overflow.ll
nand.ll
or_ops.ll
private.ll
rotate_ops.ll
select_bits.ll
sext128.ll
shift_ops.ll
shuffles.ll	Add the check to the testcase of r106419.	2010-06-21 15:11:51 +00:00
sp_farith.ll
stores.ll
storestruct.ll	"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."	2010-05-04 17:58:46 +00:00
struct_1.ll
sub_ops.ll	Fix encoding of 'sf' and 'sfh' instructions.	2010-05-10 08:13:49 +00:00
trunc.ll
vec_const.ll
vecinsert.ll	Fix SPU to cope with vector insertelement to an undef position.	2010-06-09 09:58:17 +00:00