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37549aa093
This patch is a follow up for D62018 to add lrint/llrint support for float16. Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62863 llvm-svn: 362700
36 lines
815 B
LLVM
36 lines
815 B
LLVM
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
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; CHECK-LABEL: testmhhs:
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; CHECK: frintx h0, h0
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; CHECK-NEXT: fcvtzs x0, h0
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; CHECK: ret
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define i16 @testmhhs(half %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
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%conv = trunc i64 %0 to i16
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ret i16 %conv
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}
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; CHECK-LABEL: testmhws:
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; CHECK: frintx h0, h0
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; CHECK-NEXT: fcvtzs x0, h0
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; CHECK: ret
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define i32 @testmhws(half %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmhxs:
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; CHECK: frintx h0, h0
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; CHECK-NEXT: fcvtzs x0, h0
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; CHECK: ret
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define i64 @testmhxs(half %x) {
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
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ret i64 %0
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}
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declare i64 @llvm.lrint.i64.f16(half) nounwind readnone
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