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4bf7d5872e
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
31 lines
1.4 KiB
LLVM
31 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -stack-symbol-ordering=0 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=i686-apple-darwin -stack-symbol-ordering=0 | FileCheck %s -check-prefix=X32
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%struct.Baz = type { [17 x i8] }
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%struct.__va_list_tag = type { i32, i32, i8*, i8* }
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; Function Attrs: nounwind uwtable
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define void @bar(%struct.Baz* byval(%struct.Baz) nocapture readnone align 8 %x, ...) {
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entry:
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%va = alloca [1 x %struct.__va_list_tag], align 16
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%arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0
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%arraydecay1 = bitcast [1 x %struct.__va_list_tag]* %va to i8*
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call void @llvm.va_start(i8* %arraydecay1)
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%overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0, i32 2
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%overflow_arg_area = load i8*, i8** %overflow_arg_area_p, align 8
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%overflow_arg_area.next = getelementptr i8, i8* %overflow_arg_area, i64 24
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store i8* %overflow_arg_area.next, i8** %overflow_arg_area_p, align 8
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; X32: leal 68(%esp), [[REG:%.*]]
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; X32: movl [[REG]], 16(%esp)
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; X64: leaq 256(%rsp), [[REG:%.*]]
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; X64: movq [[REG]], 184(%rsp)
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; X64: leaq 176(%rsp), %rdi
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call void @qux(%struct.__va_list_tag* %arraydecay)
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.va_start(i8*)
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declare void @qux(%struct.__va_list_tag*)
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