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b483140318
This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection. To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions. Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers. Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass. Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement. llvm-svn: 288028
149 lines
4.0 KiB
LLVM
149 lines
4.0 KiB
LLVM
; Test LOC.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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; Run the test again to make sure it still works the same even
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; in the presence of the load-store-on-condition-2 facility.
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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declare i32 @foo(i32 *)
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; Test the simple case.
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define i32 @f1(i32 %easy, i32 *%ptr, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK: clfi %r4, 42
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; CHECK: loche %r2, 0(%r3)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; ...and again with the operands swapped.
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define i32 @f2(i32 %easy, i32 *%ptr, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK: clfi %r4, 42
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; CHECK: locl %r2, 0(%r3)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %other, i32 %easy
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ret i32 %res
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}
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; Check the high end of the aligned LOC range.
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define i32 @f3(i32 %easy, i32 *%base, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK: clfi %r4, 42
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; CHECK: loche %r2, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 131071
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Check the next word up. Other sequences besides this one would be OK.
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define i32 @f4(i32 %easy, i32 *%base, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: clfi %r4, 42
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; CHECK: loche %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 131072
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Check the low end of the LOC range.
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define i32 @f5(i32 %easy, i32 *%base, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK: clfi %r4, 42
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; CHECK: loche %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 -131072
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Check the next word down, with the same comments as f4.
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define i32 @f6(i32 %easy, i32 *%base, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, -524292
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; CHECK: clfi %r4, 42
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; CHECK: loche %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 -131073
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Try a frame index base.
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define i32 @f7(i32 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: loche %r2, {{[0-9]+}}(%r15)
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; CHECK: br %r14
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%ptr = alloca i32
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%easy = call i32 @foo(i32 *%ptr)
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Try a case when an index is involved.
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define i32 @f8(i32 %easy, i32 %limit, i64 %base, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: clfi %r3, 42
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; CHECK: loche %r2, 0({{%r[1-5]}})
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; CHECK: br %r14
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%cond = icmp ult i32 %limit, 42
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%other = load i32 , i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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; Test that conditionally-executed loads do not use LOC, since it is allowed
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; to trap even when the condition is false.
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define i32 @f9(i32 %easy, i32 %limit, i32 *%ptr) {
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; CHECK-LABEL: f9:
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; CHECK-NOT: loc
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; CHECK: br %r14
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entry:
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%cmp = icmp ule i32 %easy, %limit
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br i1 %cmp, label %load, label %exit
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load:
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%other = load i32 , i32 *%ptr
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br label %exit
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exit:
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%res = phi i32 [ %easy, %entry ], [ %other, %load ]
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ret i32 %res
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}
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; Test that volatile loads do not use LOC, since if the condition is false,
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; it is unspecified whether or not the load happens. LOCR is fine though.
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define i32 @f10(i32 %easy, i32 *%ptr, i32 %limit) {
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; CHECK-LABEL: f10:
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; CHECK: l {{%r[0-9]*}}, 0(%r3)
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; CHECK: locr
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%other = load volatile i32, i32 *%ptr
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%res = select i1 %cond, i32 %easy, i32 %other
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ret i32 %res
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}
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