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From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810
24 lines
782 B
LLVM
24 lines
782 B
LLVM
; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define <4 x i32> @testi1(<4 x i32> %b1, <4 x i32> %b2) #0 {
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entry:
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%0 = call <4 x i32> asm "xxland $0, $1, $2", "=^wd,^wd,^wd"(<4 x i32> %b1, <4 x i32> %b2) #0
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ret <4 x i32> %0
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; CHECK: error: couldn't allocate output register for constraint 'wd'
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}
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define signext i32 @testi2(<4 x float> %__A) #0 {
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entry:
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%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3", "=^wi,=&^wi,^wi"(<4 x float> %__A) #0
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%asmresult = extractvalue { i32, <4 x float> } %0, 0
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ret i32 %asmresult
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; CHECK: error: couldn't allocate output register for constraint 'wi'
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}
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attributes #0 = { nounwind "target-features"="-vsx" }
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