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[PowerPC] Support constraint 'wi' in asm

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From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D53265

llvm-svn: 345810
This commit is contained in:
Li Jia He 2018-11-01 02:35:17 +00:00
parent dc5f305f29
commit 0ec2cb142d
3 changed files with 30 additions and 2 deletions
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8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -13362,7 +13362,8 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const {
} else if (Constraint == "wc") { // individual CR bits.
return C_RegisterClass;
} else if (Constraint == "wa" || Constraint == "wd" ||
Constraint == "wf" || Constraint == "ws") {
Constraint == "wf" || Constraint == "ws" ||
Constraint == "wi") {
return C_RegisterClass; // VSX registers.
}
return TargetLowering::getConstraintType(Constraint);
@ -13392,6 +13393,8 @@ PPCTargetLowering::getSingleConstraintMatchWeight(
return CW_Register;
else if (StringRef(constraint) == "ws" && type->isDoubleTy())
return CW_Register;
else if (StringRef(constraint) == "wi" && type->isIntegerTy(64))
return CW_Register; // just hold 64-bit integers data.
switch (*constraint) {
default:
@ -13474,7 +13477,8 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
// An individual CR bit.
return std::make_pair(0U, &PPC::CRBITRCRegClass);
} else if ((Constraint == "wa" || Constraint == "wd" ||
Constraint == "wf") && Subtarget.hasVSX()) {
Constraint == "wf" || Constraint == "wi") &&
Subtarget.hasVSX()) {
return std::make_pair(0U, &PPC::VSRCRegClass);
} else if (Constraint == "ws" && Subtarget.hasVSX()) {
if (VT == MVT::f32 && Subtarget.hasP8Vector())

15
test/CodeGen/PowerPC/inlineasm-vsx-reg.ll
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@ -12,6 +12,21 @@ entry:
; CHECK: #NO_APP
}
define signext i32 @foo1(<4 x float> %__A) {
entry:
%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wi,^wa"(<4 x float> %__A)
%asmresult = extractvalue { i32, <4 x float> } %0, 0
ret i32 %asmresult
; CHECK: #APP
; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: xscvspdp f0, f0
; CEHCK: fctiw f0, f0
; CHECK: mffprd r3, f0
; CEHCK: extsw r3, r3
; CHECK: #NO_APP
}
define double @test() {
entry:
%0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"()

9
test/CodeGen/PowerPC/vec-asm-disabled.ll
View File

@ -10,5 +10,14 @@ entry:
; CHECK: error: couldn't allocate output register for constraint 'wd'
}
define signext i32 @testi2(<4 x float> %__A) #0 {
entry:
%0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3", "=^wi,=&^wi,^wi"(<4 x float> %__A) #0
%asmresult = extractvalue { i32, <4 x float> } %0, 0
ret i32 %asmresult
; CHECK: error: couldn't allocate output register for constraint 'wi'
}
attributes #0 = { nounwind "target-features"="-vsx" }