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llvm-mirror/test/CodeGen/RISCV/rvv
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Fraser Cormack 100d58ed00 [RISCV] Add support for RVV int<->fp & fp<->fp conversions 
This patch adds support for the full range of vector int-to-float,
float-to-int, and float-to-float conversions on legal types.

Many conversions are supported natively in RVV so are lowered with
patterns. These include conversions between (element) types of the same
size, and those that are half/double the size of the input. When
conversions take place between types that are less than half or more
than double the size we must lower them using sequences of instructions
which go via intermediate types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95447
2021-01-28 09:50:32 +00:00
..
add-vsetvli-gpr.mir
[RISCV] Make LMUL field in VTYPE continuous.
2021-01-22 00:47:32 +08:00
add-vsetvli-vlmax.ll
[RISCV] Make LMUL field in VTYPE continuous.
2021-01-22 00:47:32 +08:00
cleanup-vsetvli.mir
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
extractelt-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
extractelt-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
extractelt-int-rv32.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
extractelt-int-rv64.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
insertelt-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
insertelt-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
insertelt-int-rv32.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
insertelt-int-rv64.ll
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
2021-01-25 22:03:52 +00:00
load-add-store-8.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-16.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-32.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
load-add-store-64.ll
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
mask-exts-truncs-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
mask-exts-truncs-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
rv32-vsetvli-intrinsics.ll
[RISCV] Add intrinsics for vsetvli instruction
2020-12-18 12:10:09 -08:00
rv64-vsetvli-intrinsics.ll
[RISCV] Add intrinsics for vsetvli instruction
2020-12-18 12:10:09 -08:00
rvv-vscale.i32.ll
[RISCV] Custom lower ISD::VSCALE.
2021-01-13 17:14:49 -08:00
rvv-vscale.i64.ll
[RISCV] Custom lower ISD::VSCALE.
2021-01-13 17:14:49 -08:00
saddo-sdnode.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
setcc-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
setcc-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
setcc-integer-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
setcc-integer-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vaadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vaadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vaaddu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vaaddu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vadd-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomaxu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomaxu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamomin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamominu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamominu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoswap-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoswap-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vamoxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vand-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vasub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vasub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vasubu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vasubu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vcompress-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vcompress-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdiv-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdiv-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdiv-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vdiv-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vdivu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdivu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vdivu-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vdivu-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vexts-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vexts-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfadd-sdnode-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfadd-sdnode-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfclass-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfclass-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfcvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfdiv-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfdiv-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfdiv-sdnode-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfdiv-sdnode-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfirst-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfirst-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmerge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmerge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfmul-sdnode-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfmul-sdnode-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfmv.f.s.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.s.f-rv32.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.s.f-rv64.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.v.f-rv32.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfmv.v.f-rv64.ll
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
vfncvt-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfnmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfpext-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfptoi-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfptrunc-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vfrdiv-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrdiv-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredosum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredosum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfrsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnj-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnj-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnjn-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnjn-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnjx-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsgnjx-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1down-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1down-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1up-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfslide1up-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsqrt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsqrt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfsub-sdnode-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfsub-sdnode-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vfwadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwadd.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwadd.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-rtz-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-x-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-x-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-xu-f-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwcvt-xu-f-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredosum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredosum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vfwsub.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vid-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vid-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
viota-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
viota-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vitofp-sdnode.ll
[RISCV] Add support for RVV int<->fp & fp<->fp conversions
2021-01-28 09:50:32 +00:00
vle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vleff-rv32.ll
[RISCV] Add a VL output to vleff intrinsics.
2021-01-21 17:19:58 -08:00
vleff-rv64.ll
[RISCV] Add a VL output to vleff intrinsics.
2021-01-21 17:19:58 -08:00
vloxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vloxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vloxseg-rv32.ll
[RISCV] Add RV32 test cases for vloxseg.
2021-01-23 08:54:56 +08:00
vloxseg-rv64.ll
[RISCV] Add RV64 test cases for vloxseg.
2021-01-23 08:54:56 +08:00
vlse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlsegff-rv32-dead.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv32.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv64-dead.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsegff-rv64.ll
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
vlsseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vlsseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vluxei-rv32.ll
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
2021-01-21 18:38:49 -08:00
vluxei-rv64.ll
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
2021-01-21 18:38:49 -08:00
vluxseg-rv32.ll
[RISCV] Add RV32 test cases for vluxseg.
2021-01-23 08:54:56 +08:00
vluxseg-rv64.ll
[RISCV] Add RV64 test cases for vluxseg.
2021-01-23 08:54:56 +08:00
vmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc.carry.in-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadc.carry.in-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmandnot-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmandnot-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmarith-sdnode.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmax-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmaxu-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmclr-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmclr-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmerge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmerge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfeq-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfeq-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfge-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfge-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfgt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfgt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmflt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmflt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfne-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmfne-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmin-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vminu-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmnor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmornot-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmornot-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc.borrow.in-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbc.borrow.in-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbf-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsbf-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmseq-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmseq-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmset-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmset-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgtu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsgtu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsif-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsif-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsle-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsle-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsleu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsleu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmslt-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmslt-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsltu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsltu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsne-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsne-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsof-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmsof-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmul-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulh-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulh-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulh-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vmulhsu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulhsu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulhu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmulhu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.s.x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.s.x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.v-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.v-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.x-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.v.x-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.x.s-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmv.x.s-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxnor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxnor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vmxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclip-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclip-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclipu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnclipu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsac-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsac-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnmsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsra-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsra-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsrl-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vnsrl-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vor-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vpopc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vpopc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredand-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredand-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmax-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmax-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmaxu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmaxu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmin-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredmin-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredminu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredminu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vredxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrem-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrem-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrem-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vrem-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vremu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vremu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vremu-sdnode-rv32.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vremu-sdnode-rv64.ll
[SelectionDAG] Support scalable-vector splats in more cases
2021-01-25 10:58:15 +00:00
vrgather-rv32.ll
[RISCV] Fix intrinsic CodeGen test cases for vrgather
2021-01-22 00:34:02 -08:00
vrgather-rv64.ll
[RISCV] Fix intrinsic CodeGen test cases for vrgather
2021-01-22 00:34:02 -08:00
vrgatherei16-rv32.ll
[RISCV] Add intrinsics for RVV 1.0 vrgatherei16
2021-01-21 18:38:49 -08:00
vrgatherei16-rv64.ll
[RISCV] Add intrinsics for RVV 1.0 vrgatherei16
2021-01-21 18:38:49 -08:00
vrsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vrsub-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsaddu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsaddu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsbc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsbc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vselect-fp-rv32.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vselect-fp-rv64.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vselect-int-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vselect-int-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsext-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsext-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vshl-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vshl-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1down-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1down-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1up-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslide1up-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslidedown-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslidedown-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslideup-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vslideup-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsll-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsll-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsoxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsoxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsoxseg-rv32.ll
[RISCV] Add RV32 test cases for vsoxseg.
2021-01-23 08:54:56 +08:00
vsoxseg-rv64.ll
[RISCV] Add RV64 test cases for vsoxseg.
2021-01-23 08:54:56 +08:00
vsplats-fp.ll
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
vsplats-i1.ll
[RISCV] Add vector mask arithmetic ISel patterns
2021-01-07 09:43:25 +00:00
vsplats-i64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsra-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsrl-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsse-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsse-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssra-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssra-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssrl-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssrl-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssseg-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssseg-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssubu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vssubu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsub-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsub-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxei-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxei-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vsuxseg-rv32.ll
[RISCV] Add RV32 test cases for vsuxseg.
2021-01-23 08:54:56 +08:00
vsuxseg-rv64.ll
[RISCV] Add RV64 test cases for vsuxseg.
2021-01-23 08:54:56 +08:00
vtruncs-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vtruncs-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwadd.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwaddu.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmacc-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmacc-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccsu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccsu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccus-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmaccus-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmul-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmul-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulsu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulsu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwmulu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsum-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsum-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsumu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwredsumu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsub.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu.w-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vwsubu.w-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vxor-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vxor-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vxor-sdnode-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vxor-sdnode-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vzext-rv32.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00
vzext-rv64.ll
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
2021-01-22 07:55:24 +08:00