Krzysztof Parzyszek 886e13050e [Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing ... Selection DAG preprocessing runs long after legalization, so make sure that the types can be handled by the selection code.		2020-02-11 15:27:33 -06:00
..
AArch64	[AArch64][SVE] Add SVE2 intrinsics for complex integer dot product	2020-02-11 10:28:31 +00:00
AMDGPU	AMDGPU: Move R600 test compatability hack	2020-02-10 10:02:06 -08:00
ARC
ARM	Revert "[ARM] Improve codegen of volatile load/store of i64"	2020-02-08 13:18:45 +00:00
AVR
BPF	[BPF] implement isTruncateFree and isZExtFree in BPFTargetLowering	2020-02-11 09:59:19 -08:00
Generic	Remove lit feature object-emission	2020-02-10 15:57:56 -06:00
Hexagon	[Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing	2020-02-11 15:27:33 -06:00
Inputs
Lanai
Mips	[Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.	2020-02-11 11:47:30 +01:00
MIR
MSP430
NVPTX
PowerPC	[AIX] Enable frame pointer for AIX and add related test suite	2020-02-10 15:43:41 -05:00
RISCV	[RISCV] Add support for save/restore of callee-saved registers via libcalls	2020-02-11 21:23:03 +00:00
SPARC
SystemZ	[SystemZ] Fix new test case for expensive checks.	2020-02-11 11:33:41 -05:00
Thumb
Thumb2	[ARM][MVE] Tail-Predication: recognise (again) active lanes IR pattern	2020-02-11 15:18:18 +00:00
VE
WebAssembly	[WebAssembly] Fix signature of __powitf2 libcall	2020-02-07 20:30:47 -08:00
WinCFGuard
WinEH
X86	[X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SSSE3 targets	2020-02-11 12:21:03 +00:00
XCore