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e9d7161099
This adds some extra patterns to select AArch64 Neon SQADD, UQADD, SQSUB and UQSUB from the existing target independent sadd_sat, uadd_sat, ssub_sat and usub_sat nodes. It does not attempt to replace the existing int_aarch64_neon_uqadd intrinsic nodes as they are apparently used for both scalar and vector, and need to be legal on scalar types for some of the patterns to work. The int_aarch64_neon_uqadd on scalar would move the two integers into floating point registers, perform a Neon uqadd and move the value back. I don't believe this is good idea for uadd_sat to do the same as the scalar alternative is simpler (an adds with a csinv). For signed it may be smaller, but I'm not sure about it being better. So this just adds some extra patterns for the existing vector instructions, matching on the _sat nodes. Differential Revision: https://reviews.llvm.org/D69374
96 lines
2.8 KiB
LLVM
96 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i4 @llvm.ssub.sat.i4(i4, i4)
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declare i8 @llvm.ssub.sat.i8(i8, i8)
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declare i16 @llvm.ssub.sat.i16(i16, i16)
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declare i32 @llvm.ssub.sat.i32(i32, i32)
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declare i64 @llvm.ssub.sat.i64(i64, i64)
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declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cinv w8, w9, ge
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; CHECK-NEXT: subs w9, w0, w1
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; CHECK-NEXT: csel w0, w8, w9, vs
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; CHECK-NEXT: ret
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: func2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: mov x9, #9223372036854775807
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; CHECK-NEXT: cmp x8, #0 // =0
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; CHECK-NEXT: cinv x8, x9, ge
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; CHECK-NEXT: subs x9, x0, x1
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; CHECK-NEXT: csel x0, x8, x9, vs
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: func16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: mov w9, #32767
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; CHECK-NEXT: sub w8, w8, w1, sxth
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: csel w8, w8, w9, lt
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; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
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; CHECK-NEXT: mov w9, #-32768
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: func8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: sub w8, w8, w1, sxtb
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; CHECK-NEXT: mov w9, #127
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; CHECK-NEXT: cmp w8, #127 // =127
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; CHECK-NEXT: csel w8, w8, w9, lt
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; CHECK-NEXT: cmn w8, #128 // =128
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; CHECK-NEXT: mov w9, #-128
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-LABEL: func3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w1, #28
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; CHECK-NEXT: sbfx w9, w0, #0, #4
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; CHECK-NEXT: sub w8, w9, w8, asr #28
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; CHECK-NEXT: mov w10, #7
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; CHECK-NEXT: cmp w8, #7 // =7
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; CHECK-NEXT: csel w8, w8, w10, lt
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; CHECK-NEXT: cmn w8, #8 // =8
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; CHECK-NEXT: mov w9, #-8
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; CHECK-NEXT: csel w0, w8, w9, gt
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; CHECK-NEXT: ret
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%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
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ret <4 x i32> %tmp;
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}
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