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https://github.com/RPCS3/llvm-mirror.git
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57458dafa4
Summary: This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]. In middle-end, we'd want to prefer the form with two adds - D63992, but as this diff shows, not every target will prefer that pattern. Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars, but only X86 prefer that same pattern for vectors. Here i'm adding a new TLI hook, always defaulting to the inc-of-add, but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars. Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel Reviewed By: efriedma Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64090 llvm-svn: 365010
96 lines
2.7 KiB
LLVM
96 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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; These two forms are equivalent:
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; sub %y, (xor %x, -1)
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; add (add %x, 1), %y
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; Some targets may prefer one to the other.
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define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: scalar_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w1, w0
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; CHECK-NEXT: add w0, w8, #1 // =1
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; CHECK-NEXT: ret
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%t0 = xor i8 %x, -1
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%t1 = sub i8 %y, %t0
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ret i8 %t1
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}
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define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: scalar_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w1, w0
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; CHECK-NEXT: add w0, w8, #1 // =1
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; CHECK-NEXT: ret
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%t0 = xor i16 %x, -1
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%t1 = sub i16 %y, %t0
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ret i16 %t1
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}
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define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: scalar_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w1, w0
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; CHECK-NEXT: add w0, w8, #1 // =1
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; CHECK-NEXT: ret
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%t0 = xor i32 %x, -1
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%t1 = sub i32 %y, %t0
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ret i32 %t1
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}
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define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scalar_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x1, x0
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; CHECK-NEXT: add x0, x8, #1 // =1
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; CHECK-NEXT: ret
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%t0 = xor i64 %x, -1
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%t1 = sub i64 %y, %t0
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ret i64 %t1
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}
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define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
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; CHECK-LABEL: vector_i128_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: sub v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%t0 = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%t1 = sub <16 x i8> %y, %t0
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ret <16 x i8> %t1
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}
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define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
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; CHECK-LABEL: vector_i128_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: sub v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%t0 = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%t1 = sub <8 x i16> %y, %t0
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ret <8 x i16> %t1
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}
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define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: vector_i128_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%t0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%t1 = sub <4 x i32> %y, %t0
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ret <4 x i32> %t1
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}
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define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
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; CHECK-LABEL: vector_i128_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: sub v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: ret
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%t0 = xor <2 x i64> %x, <i64 -1, i64 -1>
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%t1 = sub <2 x i64> %y, %t0
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ret <2 x i64> %t1
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}
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