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https://github.com/RPCS3/llvm-mirror.git
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1e7c397a16
The code paths in the absence of TargetMachine, TargetLowering or TargetRegisterInfo are poorly tested. As rL285987 said, requiring TargetPassConfig allows us to delete many (untested) checks littered everywhere. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73754
201 lines
4.3 KiB
LLVM
201 lines
4.3 KiB
LLVM
; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
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; RUN: opt -mtriple=aarch64 -codegenprepare -S < %s | llc -mtriple=aarch64 -mattr=+sve -asm-verbose=0 | FileCheck %s
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;
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; RDVL
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;
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; CHECK-LABEL: rdvl_i8:
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; CHECK: rdvl x0, #1
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; CHECK-NEXT: ret
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define i8 @rdvl_i8() nounwind {
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%vscale = call i8 @llvm.vscale.i8()
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%1 = mul nsw i8 %vscale, 16
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ret i8 %1
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}
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; CHECK-LABEL: rdvl_i16:
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; CHECK: rdvl x0, #1
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; CHECK-NEXT: ret
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define i16 @rdvl_i16() nounwind {
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%vscale = call i16 @llvm.vscale.i16()
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%1 = mul nsw i16 %vscale, 16
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ret i16 %1
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}
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; CHECK-LABEL: rdvl_i32:
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; CHECK: rdvl x0, #1
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; CHECK-NEXT: ret
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define i32 @rdvl_i32() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 16
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ret i32 %1
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}
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; CHECK-LABEL: rdvl_i64:
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; CHECK: rdvl x0, #1
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; CHECK-NEXT: ret
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define i64 @rdvl_i64() nounwind {
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%vscale = call i64 @llvm.vscale.i64()
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%1 = mul nsw i64 %vscale, 16
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ret i64 %1
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}
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; CHECK-LABEL: rdvl_const:
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; CHECK: rdvl x0, #1
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; CHECK-NEXT: ret
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define i32 @rdvl_const() nounwind {
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ret i32 mul nsw (i32 ptrtoint (<vscale x 1 x i8>* getelementptr (<vscale x 1 x i8>, <vscale x 1 x i8>* null, i64 1) to i32), i32 16)
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}
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define i32 @vscale_1() nounwind {
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; CHECK-LABEL: vscale_1:
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; CHECK: rdvl [[TMP:x[0-9]+]], #1
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; CHECK-NEXT: lsr x0, [[TMP]], #4
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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ret i32 %vscale
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}
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define i32 @vscale_neg1() nounwind {
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; CHECK-LABEL: vscale_neg1:
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; CHECK: rdvl [[TMP:x[0-9]+]], #-1
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; CHECK-NEXT: asr x0, [[TMP]], #4
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%neg = mul nsw i32 -1, %vscale
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ret i32 %neg
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}
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; CHECK-LABEL: rdvl_3:
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; CHECK: rdvl [[VL_B:x[0-9]+]], #1
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; CHECK-NEXT: lsr [[VL_Q:x[0-9]+]], [[VL_B]], #4
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; CHECK-NEXT: mov w[[MUL:[0-9]+]], #3
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; CHECK-NEXT: mul x0, [[VL_Q]], x[[MUL]]
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; CHECK-NEXT: ret
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define i32 @rdvl_3() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 3
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ret i32 %1
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}
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; CHECK-LABEL: rdvl_min:
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; CHECK: rdvl x0, #-32
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; CHECK-NEXT: ret
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define i32 @rdvl_min() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, -512
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ret i32 %1
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}
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; CHECK-LABEL: rdvl_max:
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; CHECK: rdvl x0, #31
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; CHECK-NEXT: ret
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define i32 @rdvl_max() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 496
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ret i32 %1
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}
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;
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; CNTH
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;
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; CHECK-LABEL: cnth:
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; CHECK: cnth x0{{$}}
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; CHECK-NEXT: ret
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define i32 @cnth() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = shl nsw i32 %vscale, 3
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ret i32 %1
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}
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; CHECK-LABEL: cnth_max:
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; CHECK: cnth x0, all, mul #15
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; CHECK-NEXT: ret
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define i32 @cnth_max() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 120
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ret i32 %1
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}
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; CHECK-LABEL: cnth_neg:
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; CHECK: cnth [[CNT:x[0-9]+]]
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; CHECK: neg x0, [[CNT]]
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; CHECK-NEXT: ret
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define i32 @cnth_neg() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, -8
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ret i32 %1
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}
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;
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; CNTW
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;
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; CHECK-LABEL: cntw:
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; CHECK: cntw x0{{$}}
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; CHECK-NEXT: ret
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define i32 @cntw() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = shl nsw i32 %vscale, 2
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ret i32 %1
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}
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; CHECK-LABEL: cntw_max:
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; CHECK: cntw x0, all, mul #15
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; CHECK-NEXT: ret
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define i32 @cntw_max() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 60
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ret i32 %1
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}
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; CHECK-LABEL: cntw_neg:
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; CHECK: cntw [[CNT:x[0-9]+]]
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; CHECK: neg x0, [[CNT]]
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; CHECK-NEXT: ret
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define i32 @cntw_neg() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, -4
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ret i32 %1
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}
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;
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; CNTD
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;
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; CHECK-LABEL: cntd:
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; CHECK: cntd x0{{$}}
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; CHECK-NEXT: ret
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define i32 @cntd() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = shl nsw i32 %vscale, 1
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ret i32 %1
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}
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; CHECK-LABEL: cntd_max:
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; CHECK: cntd x0, all, mul #15
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; CHECK-NEXT: ret
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define i32 @cntd_max() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, 30
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ret i32 %1
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}
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; CHECK-LABEL: cntd_neg:
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; CHECK: cntd [[CNT:x[0-9]+]]
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; CHECK: neg x0, [[CNT]]
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; CHECK-NEXT: ret
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define i32 @cntd_neg() nounwind {
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%vscale = call i32 @llvm.vscale.i32()
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%1 = mul nsw i32 %vscale, -2
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ret i32 %1
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}
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declare i8 @llvm.vscale.i8()
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declare i16 @llvm.vscale.i16()
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declare i32 @llvm.vscale.i32()
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declare i64 @llvm.vscale.i64()
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