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207f6805ea
The code for duplicating instructions could sometimes try to emit copies intended to deal with unconstrainable register classes to the tail block of the original instruction, rather than before the newly cloned instruction in the predecessor block. This was exposed by GlobalISel on arm64. Differential Revision: https://reviews.llvm.org/D64049 llvm-svn: 364888
126 lines
3.8 KiB
YAML
126 lines
3.8 KiB
YAML
# RUN: llc -mtriple aarch64 -run-pass=early-tailduplication -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
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---
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name: pluto
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tracksRegLiveness: true
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body: |
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; This test checks that the COPY3 and COPY4 copies are correctly placed in the bb.5 block,
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; instead of crashing.
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; CHECK-LABEL: name: pluto
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:gpr32common = IMPLICIT_DEF
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; CHECK: [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK: [[DEF3:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
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; CHECK: TBNZW [[DEF]], 0, %bb.1
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; CHECK: B %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[DEF3]], 0 :: (load 8 from `i64* undef`)
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; CHECK: B %bb.9
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x40000000), %bb.4(0x40000000)
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; CHECK: $wzr = SUBSWri [[DEF1]], 19, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: TBNZW [[CSINCWr]], 0, %bb.3
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; CHECK: B %bb.4
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; CHECK: bb.3:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[DEF2]]
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[SCVTFUXDri]]
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[SCVTFUXDri]]
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; CHECK: B %bb.9
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; CHECK: bb.4:
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; CHECK: successors: %bb.5(0x40000000), %bb.8(0x40000000)
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; CHECK: TBNZW [[DEF]], 0, %bb.5
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; CHECK: B %bb.8
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; CHECK: bb.5:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[DEF2]]
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; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
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; CHECK: [[COPY4:%[0-9]+]]:fpr64 = COPY [[DEF2]]
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; CHECK: B %bb.9
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; CHECK: bb.8:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: bb.9:
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; CHECK: [[PHI:%[0-9]+]]:gpr64 = PHI [[LDRXui]], %bb.1, [[FMOVD0_]], %bb.8, [[COPY]], %bb.3, [[COPY3]], %bb.5
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $d0 = COPY [[PHI]]
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; CHECK: BL @pluto, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $w0 = COPY [[MOVi32imm]]
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; CHECK: RET_ReallyLR implicit $w0
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bb.1:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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liveins: $x0
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%1:gpr32 = IMPLICIT_DEF
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%2:gpr32common = IMPLICIT_DEF
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%5:gpr64 = IMPLICIT_DEF
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%9:gpr64common = IMPLICIT_DEF
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%13:gpr32 = MOVi32imm 1
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%14:fpr64 = FMOVD0
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TBNZW %1, 0, %bb.2
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B %bb.3
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bb.2:
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successors: %bb.8(0x80000000)
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%8:gpr64 = LDRXui %9, 0 :: (load 8 from `i64* undef`)
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B %bb.8
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bb.3:
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successors: %bb.4(0x40000000), %bb.5(0x40000000)
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$wzr = SUBSWri %2, 19, 0, implicit-def $nzcv
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%15:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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TBNZW %15, 0, %bb.4
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B %bb.5
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bb.4:
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successors: %bb.7(0x80000000)
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%6:fpr64 = SCVTFUXDri %5
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B %bb.7
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bb.5:
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successors: %bb.6(0x40000000), %bb.9(0x40000000)
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TBNZW %1, 0, %bb.6
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B %bb.9
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bb.6:
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successors: %bb.7(0x80000000)
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bb.7:
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successors: %bb.8(0x80000000)
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%7:fpr64 = PHI %6, %bb.4, %5, %bb.6
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bb.8:
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successors: %bb.10(0x80000000)
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%10:gpr64 = PHI %8, %bb.2, %7, %bb.7
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B %bb.10
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bb.9:
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successors: %bb.10(0x80000000)
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bb.10:
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%11:gpr64 = PHI %10, %bb.8, %14, %bb.9
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ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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$d0 = COPY %11
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BL @pluto, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
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ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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$w0 = COPY %13
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RET_ReallyLR implicit $w0
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...
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