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https://github.com/RPCS3/llvm-mirror.git
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5f91239343
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
207 lines
7.1 KiB
LLVM
207 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> %a)
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declare i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> %a)
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define i32 @reduce_and_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smov w8, v0.b[0]
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: csel w0, w0, w1, lt
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; CHECK-NEXT: ret
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%x = icmp slt <1 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #24
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; CHECK-NEXT: sshr v0.2s, v0.2s, #24
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; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
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; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <2 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v2i1(<2 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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; CHECK-NEXT: uminv h0, v0.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <4 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: uminv b0, v0.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <8 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v8i1(<8 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: uminv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <16 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v16i1(<16 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_and_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_and_v32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: uminv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <32 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.and.v32i1(<32 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v1(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smov w8, v0.b[0]
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: csel w0, w0, w1, lt
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; CHECK-NEXT: ret
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%x = icmp slt <1 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v1i1(<1 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v2(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #24
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; CHECK-NEXT: sshr v0.2s, v0.2s, #24
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; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
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; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <2 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v2i1(<2 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v4(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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; CHECK-NEXT: umaxv h0, v0.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <4 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v4i1(<4 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: umaxv b0, v0.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <8 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v8i1(<8 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v16(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: umaxv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <16 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v16i1(<16 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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define i32 @reduce_or_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
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; CHECK-LABEL: reduce_or_v32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: umaxv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csel w0, w0, w1, ne
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; CHECK-NEXT: ret
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%x = icmp slt <32 x i8> %a0, zeroinitializer
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%y = call i1 @llvm.experimental.vector.reduce.or.v32i1(<32 x i1> %x)
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%z = select i1 %y, i32 %a1, i32 %a2
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ret i32 %z
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}
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