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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
28 lines
815 B
LLVM
28 lines
815 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64
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define i32 @pr32690(i32) {
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; X86-LABEL: pr32690:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: addl $63, %ecx
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; X86-NEXT: setb %al
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; X86-NEXT: shldl $26, %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: pr32690:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: addq $63, %rax
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; X64-NEXT: shrq $6, %rax
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; X64-NEXT: # kill: def $eax killed $eax killed $rax
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; X64-NEXT: retq
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%2 = zext i32 %0 to i64
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%3 = add nuw nsw i64 %2, 63
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%4 = lshr i64 %3, 6
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%5 = trunc i64 %4 to i32
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ret i32 %5
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}
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