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17c114f241
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
35 lines
1.1 KiB
Plaintext
35 lines
1.1 KiB
Plaintext
# RUN: not llvm-mc -disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 2>&1 | FileCheck %s
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#------------------------------------------------------------------------------
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# Undefined encodings for mrs
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#------------------------------------------------------------------------------
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# invalid SYSm
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
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[0xef 0xf3 0x80 0x80]
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#------------------------------------------------------------------------------
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# Undefined encodings for msr
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#------------------------------------------------------------------------------
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# invalid mask = '00'
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
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[0x80 0xf3 0x00 0x80]
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# invalid mask = '11' with SYSm not in {0..3}
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x04 0x8c]
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[0x80 0xf3 0x04 0x8c]
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# invalid mask = '01' (Cortex-M3 does not have the DSP extension)
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x00 0x84]
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[0x80 0xf3 0x00 0x84]
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# invalid SYSm
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
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[0x80 0xf3 0x80 0x88]
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